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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
3807
Group
User's Manual
keep safety first in your circuit designs ! q Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials q These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. q Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. q All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. q Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. q The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. q If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of JAPAN and/or the country of destination is prohibited. q Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Preface
This user's manual describes Mitsubishi's CMOS 8bit microcomputers 3807 Group. After reading this manual, the user should have a through knowledge of the functions and features of the 3807 Group, and should be able to fully utilize the product. The manual starts with specifications and ends with application examples. For details of software, refer to the "SERIES MELPS 740 USER'S MANUAL." For details of development support tools, refer to the "DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS" data book.
BEFORE USING THIS USER'S MANUAL
This user's manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. Chapter 3 also includes necessary information for systems denelopment. Be sure to refer to this chapter.
1. Organization
q CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. q CHAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, electric characteristics, a list of registers, the masking confirmation (mask ROM version), and mark specifications which are to be submitted when ordering.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bits
b7 b6 b5 b4 b3 b2 b1 b0 0
Bit attributes
(Note 1)
Contents immediately after reset release
CPU mode register (CPUM) [Address : 3B16] B 0 1 2 3 4 5 6 7 Stack page selection bit Name
b1 b0
Function
0 0 : Single-chip mode 01: 1 0 : Not available 11: 0 : 0 page 1 : 1 page
At reset
RW
Processor mode bits
0 0 0 0 0 1
T T
Nothing arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0." Fix this bit to "0." Main clock (XIN-XOUT) stop bit Internal system clock selection bit
0 : Operating 1 : Stopped 0 : XIN-XOUT selected 1 : XCIN-XCOUT selected
! !
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Note 1. Contents immediately after reset release 0******"0" at reset release 1******"1" at reset release Undefined******Undefined or reset release T ******Contents determined by option at reset release Note 2. Bit attributes******The attributes of control register bits are classified into 3 bytes : read-only, write-only and read and write. In the figure, these attributes are represented as follows : R******Read ******Read enabled !******Read disabled W******Write ******Write enabled ! ******Write disabled
LIST OF GROUPS HAVING THE SIMILAR FUNCTIONS
3807 group, one of the CMOS 8-bit microcomputer 38000 series presented in this user's manual is provided with standard functions. The basic functions of the 3800, 3802, 3806 and 3807 groups having the same functions are shown below. For the detailed functions of each group, refer to the related data book and user's manual.
List of groups having the same functions
Group Function Pin (Package type) 3800 group
64 pin * 64P4B * 64P6N-A * 64P6D-A
As of September 1996 3806 group
80 pin * 80P6N-A * 80P6S-A * 80P6D-A
3802 group
64 pin * 64P4B * 64P6N-A
3807 group
80 pin * 80P6N-A
Clock generating circuit
1 circuit
1 circuit
1 circuit
2 circuits
<8-bit>
Timer
<8-bit> Prescaler : 3 Timer : 4
<8-bit> Prescaler : 3 Timer : 4
<8-bit> Prescaler : 3 Timer : 4
Timer : 3 <16-bit> Timer X/Y : 2 Timer A/B : 2 UART or Clock synchronous ! 1 Clock synchronous ! 1 8-bit ! 13-channel
UART or Clock synchronous ! 1
UART or Clock synchronous ! 1 Clock synchronous ! 1 8-bit ! 8-channel
UART or Clock synchronous ! 1 Clock synchronous ! 1 8-bit ! 8-channel
Serial I/O -- A-D converter D-A converter Mask ROM Memory type One Time PROM EPROM RAM -- --
8K 16K 24K 32K (Note 1) (Note 1) V 8K
(Note 1)
8-bit ! 2-channel 16K
(Note 1)
8-bit ! 2-channel
8-bit ! 4-channel 16K 16K 16K 512 Real time port output Analog comparator Watchdog timer
(Note 1)
24K
32K 12K 16K 24K 32K 48K
(Note 1) (Note 1) (Note 1) (Note 3) (Note 3) (Note 3)
16K 8K (Note 1) -- 32K --
-- --
-- --
384
-- --
64 0
32K
(Note 1)
-- --
-- 24K -- 48K
(Note 2)
(Note 3)
-- 16K --
32 K
--
32K
--
24 K
48K -- (Note 2)
384 384 512 640 384 384
1024 384 384 512 1024 1024
PWM output
Remarks
Notes 1: 2: 3: V.
Extended operating temperature version available High-speed version available Extended operating temperature version and High-speed version available ROM expansion
Table of contents
Table of contents
CHAPTER 1. HARDWARE
DESCRIPTION ................................................................................................................................ 1-2 FEATURES ...................................................................................................................................... 1-2 APPLICATION ................................................................................................................................. 1-2 PIN CONFIGURATION ................................................................................................................... 1-2 FUNCTIONAL BLOCK ................................................................................................................... 1-3 PIN DESCRIPTION ......................................................................................................................... 1-4 PART NUMBERING ....................................................................................................................... 1-6 GROUP EXPANSION ..................................................................................................................... 1-7 FUNCTIONAL DESCRIPTION ....................................................................................................... 1-8 Central Processing Unit (CPU) ............................................................................................... 1-8 Memory .................................................................................................................................... 1-12 I/O Ports .................................................................................................................................. 1-14 Interrupts .................................................................................................................................. 1-20 Timers ...................................................................................................................................... 1-23 Serial I/O.................................................................................................................................. 1-41 A-D Converter ......................................................................................................................... 1-47 D-A Converter ......................................................................................................................... 1-48 Analog Comparator ................................................................................................................. 1-49 Watchdog Timer ...................................................................................................................... 1-50 Clock output function ............................................................................................................. 1-51 Reset Circuit ............................................................................................................................ 1-52 Clock Generating Circuit ........................................................................................................ 1-54 Processor Mode ...................................................................................................................... 1-57 NOTES ON PROGRAMMING ..................................................................................................... 1-59 Processor Status Register ..................................................................................................... 1-59 Interrupts .................................................................................................................................. 1-59 Decimal Calculations .............................................................................................................. 1-59 Timers ...................................................................................................................................... 1-59 Multiplication and Division Instructions ................................................................................ 1-59 Ports ......................................................................................................................................... 1-59 Serial I/O.................................................................................................................................. 1-59 A-D Converter ......................................................................................................................... 1-59 D-A Converter ......................................................................................................................... 1-59 Instruction Execution Time .................................................................................................... 1-59 NOTES ON USAGE ..................................................................................................................... 1-60 Handling of Source Pins ........................................................................................................ 1-60
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Table of contents
P34 clock output function ....................................................................................................... 1-60 Timer X and timer Y .............................................................................................................. 1-60 EPROM version/One Time PROM version ..........................................................................1-60 DATA REQUIRED FOR MASK ORDERS .................................................................................1-61 ROM PROGRAMMING METHOD ............................................................................................... 1-61 FUNCTIONAL DESCRIPTION SUPPLEMENT ..........................................................................1-62 Interrupt .................................................................................................................................... 1-62 Timing After Interrupt ............................................................................................................. 1-63 A-D Converter ......................................................................................................................... 1-64
CHAPTER 2. APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2 2.1.1 Memory map of I/O port ................................................................................................ 2-2 2.1.2 Related registers ............................................................................................................. 2-3 2.1.3 Handling of unused pins ................................................................................................ 2-5 2.2 Timer ......................................................................................................................................... 2-6 2.2.1 Memory map of timer ..................................................................................................... 2-6 2.2.2 Related registers ............................................................................................................. 2-7 2.2.3 Timer application examples ......................................................................................... 2-14 2.3 Serial I/O ................................................................................................................................ 2-29 2.3.1 Memory map of serial I/O ........................................................................................... 2-29 2.3.2 Related registers ........................................................................................................... 2-30 2.3.3 Serial I/O connection examples .................................................................................. 2-37 2.3.4 Setting of serial I/O transfer data format ................................................................. 2-39 2.3.5 Serial I/O application examples .................................................................................. 2-40 2.4 Real 2.4.1 2.4.2 2.4.3 time output port .......................................................................................................... 2-62 Memory map of real time output port ....................................................................... 2-62 Related registers ........................................................................................................... 2-62 Real time output port application examples ............................................................. 2-67
2.5 A-D converter ........................................................................................................................ 2-80 2.5.1 Memory map of A-D conversion .................................................................................2-80 2.5.2 Related registers ........................................................................................................... 2-81 2.5.3 A-D conversion application example ..........................................................................2-83 2.6 Reset ....................................................................................................................................... 2-87 2.6.1 Connection example of reset IC .................................................................................2-87 2.7 Application circuit example ............................................................................................... 2-88
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3807 GROUP USER'S MANUAL
Table of contents
CHAPTER 3. APPENDIX
3.1 Electrical characteristics ...................................................................................................... 3-2 3.1.1 Absolute maximum ratings ............................................................................................ 3-2 3.1.2 Recommended operating conditions............................................................................. 3-3 3.1.3 Electrical characteristics................................................................................................. 3-5 3.1.4 A-D converter characteristics ........................................................................................ 3-7 3.1.5 D-A converter characteristics ........................................................................................ 3-7 3.1.6 Analog comparator characteristics ................................................................................ 3-7 3.1.7 Timing requirements ....................................................................................................... 3-8 3.1.8 Switching characteristics ................................................................................................ 3-9 3.1.9 Timing requirements in memory expansion and microprocessor mode ............... 3-10 3.1.10 Switching characteristics in memory expansion and microprocessor mode ...... 3-10 3.2 Standard characteristics..................................................................................................... 3-17 3.2.1 Power source current characteristic examples ........................................................ 3-17 3.2.2 Port standard characteristic examples ...................................................................... 3-18 3.2.3 Input current standard characteristic examples ....................................................... 3-21 3.2.4 A-D conversion standard characteristics .................................................................. 3-22 3.2.5 D-A conversion standard characteristics .................................................................. 3-23 3.3 Notes on use......................................................................................................................... 3-24 3.3.1 Notes on interrupts ....................................................................................................... 3-24 3.3.2 Notes on the serial I/O1 .............................................................................................. 3-24 3.3.3 Notes on the A-D converter ........................................................................................ 3-25 3.3.4 Notes on the RESET pin ............................................................................................. 3-26 3.3.5 Notes on input and output pins .................................................................................. 3-26 3.3.6 Notes on memory expansion mode and microprocessor mode ............................ 3-27 3.3.7 Notes on built-in PROM ............................................................................................... 3-28 3.4 Countermeasures against noise ....................................................................................... 3-29 3.4.1 Shortest wiring length .................................................................................................. 3-29 3.4.2 Connection of a bypass capacitor across the Vss line and the Vcc line ............ 3-30 3.4.3 Wiring to analog input pins ......................................................................................... 3-31 3.4.4 Consideration for oscillator .......................................................................................... 3-31 3.4.5 Setup for I/O ports ....................................................................................................... 3-32 3.4.6 Providing of watchdog timer function by software .................................................. 3-32 3.5 List of registers .................................................................................................................... 3-34 3.6 Mask ROM ordering method .............................................................................................. 3-56 3.7 Mark specification form ...................................................................................................... 3-58 3.8 Package outline .................................................................................................................... 3-59 3.9 Machine Instructions ........................................................................................................... 3-60 3.10 List of instruction codes .................................................................................................. 3-70 3.11 SFR memory map .............................................................................................................. 3-71 3.12 Pin configuration ................................................................................................................ 3-72
3807 GROUP USER'S MANUAL
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List of figures
List of figures
CHAPTER 1 HARDWARE
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 Pin configuration of M38073M4-XXXFP ........................................................................... 1-2 2 Functional block diagram ................................................................................................... 1-3 3 Part numbering .................................................................................................................... 1-6 4 Memory expansion plan ..................................................................................................... 1-7 5 740 Family CPU register structure ................................................................................... 1-8 6 Register push and pop at interrupt generation and subroutine call ............................ 1-9 7 Structure of CPU mode register...................................................................................... 1-11 8 Memory map diagram ....................................................................................................... 1-12 9 Memory map of special function register (SFR) .......................................................... 1-13 10 Structure of Port P2P3 control register ....................................................................... 1-14 11 Structure of Pull-up control register .............................................................................1-14 12 Port block diagram (1) ................................................................................................... 1-17 13 Port block diagram (2) ................................................................................................... 1-18 14 Port block diagram (3) ................................................................................................... 1-19 15 Interrupt control ............................................................................................................... 1-22 16 Structure of interrupt-related registers ........................................................................ 1-22 17 Block diagram of Timer X and Timer Y ...................................................................... 1-27 18 Structure of Timer X mode register, Timer Y mode register, and Timer XY control register ............ 1-28 19 Timing chart of Timer * Event counter mode ............................................................. 1-29 20 Timing chart of Pulse output mode .............................................................................. 1-29 21 Timing chart of Pulse period measurement mode ..................................................... 1-30 22 Timing chart of Pulse width measurement mode ...................................................... 1-30 23 Timing chart of Programmable waveform generating mode ..................................... 1-31 24 Timing chart of Programmable one-shot generating mode ...................................... 1-31 25 Timing chart of PWM mode ........................................................................................... 1-32 26 Structure of Timer 123 mode register ..........................................................................1-33 27 Block diagram of Timer .................................................................................................. 1-33 28 Block diagram of Real time output port ...................................................................... 1-36 29 Structure of Real time output port related register (1) ............................................. 1-37 30 Structure of Real time output port related register (2) ............................................. 1-38 31 8 repeated load mode operation ................................................................................... 1-39 32 6 repeated load mode operation ................................................................................... 1-39 33 5 repeated load mode operation ................................................................................... 1-40 34 One-shot pulse generating mode operation ............................................................... 1-40 35 Block diagram of clock synchronous serial I/O1........................................................ 1-41 36 Operation of clock synchronous serial I/O1 function ................................................ 1-41 37 Block diagram of UART serial I/O1 .............................................................................. 1-42 38 Operation of UART serial I/O1 function ...................................................................... 1-42 39 Structure of Serial I/O1 related register...................................................................... 1-43 40 Structure of Serial I/O2 control register 1, 2 ............................................................. 1-44 41 Block diagram of Serial I/O2 ......................................................................................... 1-45 42 Timing of Serial I/O2 ...................................................................................................... 1-45 43 SCMP2 output operation ................................................................................................... 1-46 44 Structure of A-D control register ................................................................................... 1-47 45 Block diagram of A-D converter ....................................................................................1-47
3807 GROUP USER'S MANUAL
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List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Structure of D-A control register ...................................................................................1-48 Block diagram of D-A converter ....................................................................................1-48 Equivalent connection circuit of D-A converter .......................................................... 1-48 Block diagram of Analog comparator ........................................................................... 1-49 Block diagram of Watchdog timer .................................................................................1-50 Structure of Watchdog timer control register ............................................................. 1-50 Structure of Port P2P3 control register ....................................................................... 1-51 Block diagram of Clock output function ...................................................................... 1-51 Reset circuit example ..................................................................................................... 1-52 Reset sequence ............................................................................................................... 1-52 Internal status at reset ................................................................................................... 1-53 Ceramic resonator circuit ............................................................................................... 1-54 External clock input circuit .............................................................................................1-54 System clock generating circuit block diagram (Single-chip mode) .............................. 1-55 State transitions of system clock ................................................................................................. 1-56 Memory maps in various processor modes ................................................................ 1-57 Structure of CPU mode register ....................................................................................1-57 ONW function timing ....................................................................................................... 1-58 Programming and testing of One Time PROM version ............................................ 1-61 Timing chart after an interrupt occurs ..........................................................................1-63 Time up to execution of the interrupt processing routine ........................................ 1-63 A-D conversion equivalent circuit .................................................................................. 1-65 A-D conversion timing chart .......................................................................................... 1-65
CHAPTER 2 APPLICATION
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Memory map of I/O port related registers .................................................................2-2 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 7, 8) ........................................................... 2-3 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 7, 8) ............................ 2-3 Structure of Port P6 ..................................................................................................... 2-4 Structure of Port P6 direction register ....................................................................... 2-4
2.2.1 Memory map of timer related registers ......................................................................2-6 2.2.2 Structure of Timer XY control register ....................................................................... 2-7 2.2.3 Structure of Timer X Low-order, Timer X High-order, Timer Y Low-order, Timer Y High-order .... 2-7 2.2.4 Structure of Timer 1, Timer 3 ..................................................................................... 2-8 2.2.5 Structure of Timer 2 ..................................................................................................... 2-8 2.2.6 Structure of Timer X mode register ........................................................................... 2-9 2.2.7 Structure of Timer Y mode register ........................................................................... 2-9 2.2.8 Structure of Timer 123 mode register ..................................................................... 2-11 2.2.9 Structure of Interrupt edge selection register ........................................................ 2-11 2.2.10 Structure of Interrupt request register 1 ............................................................... 2-12 2.2.11 Structure of Interrupt request register 2 ............................................................... 2-12 2.2.12 Structure of Interrupt control register 1 ................................................................ 2-13 2.2.13 Structure of Interrupt control register 2 ................................................................ 2-13 2.2.14 Connection of timers and setting of division ratios [Clock function] ................ 2-15 2.2.15 Setting of related registers [Clock function] ......................................................... 2-16 2.2.16 Control procedure [Clock function] ........................................................................ 2-17 2.2.17 Example of a peripheral circuit ...............................................................................2-18 2.2.18 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output] ........... 2-18
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3807 GROUP USER'S MANUAL
List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.2.19 2.2.20 2.2.21 2.2.22 2.2.23 2.2.24 2.2.25 2.2.26 2.2.27 2.2.28 Setting of related registers [Piezoelectric buzzer output]................................... 2-19 Control procedure [Piezoelectric buzzer output] .................................................. 2-20 A method for judging if input pulse exists ........................................................... 2-21 Setting of related registers (1) [Measurement of frequency] ............................. 2-22 Setting of related registers (2) [Measurement of frequency] ............................. 2-23 Control procedure [Measurement of frequency]................................................... 2-24 Connection of the timer and setting of the division ratio [Measurement of pulse width] ........... 2-25 Setting of related registers [Measurement of pulse width] ................................ 2-26 Control procedure (1) [Measurement of pulse width] ......................................... 2-27 Control procedure (2) [Measurement of pulse width] ......................................... 2-28
2.3.1 Memory map of serial I/O related registers ........................................................... 2-29 2.3.2 Structure of Transmit/Receive buffer register ........................................................ 2-30 2.3.3 Structure of Serial I/O1 status register ................................................................... 2-30 2.3.4 Structure of Serial I/O1 control register.................................................................. 2-31 2.3.5 Structure of UART control register ........................................................................... 2-31 2.3.6 Structure of Baud rate generator .............................................................................. 2-32 2.3.7 Structure of Serial I/O2 control register 1 .............................................................. 2-32 2.3.8 Structure of Serial I/O2 control register 2 .............................................................. 2-33 2.3.9 Structure of Serial I/O2 register................................................................................ 2-33 2.3.10 Structure of Interrupt edge selection register ...................................................... 2-34 2.3.11 Structure of Interrupt request register 1 ............................................................... 2-35 2.3.12 Structure of Interrupt request register 2 ............................................................... 2-35 2.3.13 Structure of Interrupt control register 1 ................................................................ 2-36 2.3.14 Structure of Interrupt control register 2 ................................................................ 2-36 2.3.15 Serial I/O connection examples (1) ....................................................................... 2-37 2.3.16 Serial I/O connection examples (2) ....................................................................... 2-38 2.3.17 Setting of Serial I/O transfer data format ............................................................. 2-39 2.3.18 Connection diagram [Communication using a clock synchronous serial I/O] .. 2-40 2.3.19 Timing chart [Communication using a clock synchronous serial I/O] ............... 2-40 2.3.20 Setting of related registers at a transmitting side [Communication using a clock synchronous serial I/O] ................................ 2-41 2.3.21 Setting of related registers at a receiving side [Communication using a clock synchronous serial I/O] ................................ 2-42 2.3.22 Control procedure at a transmitting side [Communication using a clock synchronous serial I/O] .................................. 2-43 2.3.23 Control procedure at a receiving side [Communication using a clock synchronous serial I/O] .................................. 2-44 2.3.24 Connection diagram [Output of serial data] ......................................................... 2-45 2.3.25 Timing chart [Output of serial data] ...................................................................... 2-45 2.3.26 Setting of serial I/O1 related registers [Output of serial data] .......................... 2-46 2.3.27 Setting of serial I/O1 transmission data [Output of serial data]........................ 2-47 2.3.28 Control procedure of serial I/O1 [Output of serial data] .................................... 2-48 2.3.29 Setting of serial I/O2 related registers [Output of serial data] .......................... 2-49 2.3.30 Setting of serial I/O2 transmission data [Output of serial data]........................ 2-50 2.3.31 Control procedure of serial I/O2 [Output of serial data] .................................... 2-51 2.3.32 Connection diagram [Cyclic transmission or reception of block data between microcomputers].. 2-52 2.3.33 Timing chart [Cyclic transmission or reception of block data between microcomputers].. 2-53
3807 GROUP USER'S MANUAL
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List of figures
Fig. 2.3.34 Setting of related registers [Cyclic transmission or reception of block data between microcomputers] .. 2-53 Fig. 2.3.35 Control in the master unit ....................................................................................... 2-54 Fig. 2.3.36 Control in the slave unit .......................................................................................... 2-55 Fig. 2.3.37 Connection diagram [Communication using UART] ............................................ 2-56 Fig. 2.3.38 Timing chart [Communication using UART] ......................................................... 2-56 Fig. 2.3.39 Setting of related registers at a transmitting side [Communication using UART] ........................ 2-58 Fig. 2.3.40 Setting of related registers at a receiving side [Communication using UART] ............................ 2-59 Fig. 2.3.41 Control procedure at a transmitting side [Communication using UART] .......... 2-60 Fig. 2.3.42 Control procedure at a receiving side [Communication using UART] .............. 2-61 Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.4.1 Memory map of real time output port related registers ........................................ 2-62 2.4.2 Structure of Real time port register ........................................................................ 2-62 2.4.3 Structure of Real time port control register 0 ........................................................ 2-63 2.4.4 Structure of Real time port control register 1 ........................................................ 2-64 2.4.5 Structure of Real time port control register 2 ........................................................ 2-65 2.4.6 Structure of Real time port control register 3 ........................................................ 2-66 2.4.7 Structure of Timer A Low-order, Timer A High-order, Timer B Low-order, Timer B High-order .. 2-66 2.4.8 Connection diagram .................................................................................................... 2-67 2.4.9 Operation patterns of motor ......................................................................................2-67 2.4.10 Example of timer table for acceleration and deceleration.................................. 2-68 2.4.11 Example of operation pattern table ....................................................................... 2-69 2.4.12 Example of output data table .................................................................................. 2-69 2.4.13 Timing of Real time output ......................................................................................2-70 2.4.14 Setting method and output timing ..........................................................................2-71 2.4.15 Setting of related registers (1) ................................................................................ 2-72 2.4.16 Setting of related registers (2) ................................................................................ 2-73 2.4.17 Setting of related registers (3) ................................................................................ 2-74 2.4.18 Setting of related registers (4) ................................................................................ 2-75 2.4.19 Control procedure (1) ............................................................................................... 2-76 2.4.20 Control procedure (2) ............................................................................................... 2-77 2.4.21 Control procedure (3) ............................................................................................... 2-78 2.4.22 Control procedure (4) ............................................................................................... 2-79 2.5.1 Memory map of A-D conversion related registers ................................................. 2-80 2.5.2 Structure of A-D control register ...............................................................................2-81 2.5.3 Structure of A-D conversion register ....................................................................... 2-81 2.5.4 Structure of Interrupt request register 2 ................................................................. 2-82 2.5.5 Structure of Interrupt control register 2 .................................................................. 2-82 2.5.6 Connection diagram [Read for analog signal using an internal trigger] ............. 2-83 2.5.7 Setting of related registers [Read for analog signal using an internal trigger] . 2-83 2.5.8 Control procedure [Read for analog signal using an internal trigger] ................ 2-84 2.5.9 Connection diagram [Read for analog signal using an external trigger] ............ 2-85 2.5.10 Setting of related registers [Read for analog signal using an external trigger] ................. 2-85 2.5.11 Control procedure [Read for analog signal using an external trigger] ............. 2-86
Fig. 2.6.1 Example of Poweron reset circuit .............................................................................2-87 Fig. 2.6.2 RAM back-up system ................................................................................................. 2-87 Fig. 2.7.1 Hot water supply system application example ....................................................... 2-89 Fig. 2.7.2 CD changer (car audio) application example ......................................................... 2-90 Fig. 2.7.3 Hot water washing toilet seat application example ............................................... 2-91
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3807 GROUP USER'S MANUAL
List of figures CHAPTER 3 APPENDIX
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 Circuit for measuring output switching characteristics (1) .................................... 3-11 Circuit for measuring output switching characteristics (2) .................................... 3-11 Timing diagram (1) (in single-chip mode) .............................................................. 3-12 Timing diagram (2) (in memory expansion mode and microprocessor mode) .. 3-13 Timing diagram (3) (in memory expansion mode and microprocessor mode) .. 3-14 Timing diagram (4) (in memory expansion mode and microprocessor mode) .. 3-15 Timing diagram (5) (in memory expansion mode and microprocessor mode) .. 3-16
3.2.1 Power source current characteristic example ........................................................ 3-17 3.2.2 Power source current characteristic example (in wait mode) .............................. 3-17 3.2.3 Standard characteristic example of CMOS output port at P-channel drive(1) .. 3-18 3.2.4 Standard characteristic example of CMOS output port at P-channel drive(2) .. 3-18 3.2.5 Standard characteristic example of CMOS output port at N-channel drive(1) .. 3-19 3.2.6 Standard characteristic example of CMOS output port at N-channel drive(2) .. 3-19 3.2.7 Standard characteristic example of CMOS output port at N-channel drive(3) .. 3-20 3.2.8 Standard characteristic example of CMOS output port at N-channel drive(4) .. 3-20 3.2.9 Standard characteristic example of input current at connecting pull-up transistor (1) .................. 3-21 3.2.10 Standard characteristic example of input current at connecting pull-up transistor (2) ................ 3-21 3.2.11 A-D conversion standard characteristics .............................................................. 3-22 3.2.12 D-A conversion standard characteristics .............................................................. 3-23
Fig. 3.3.1 Structure of interrupt control register 2 .................................................................. 3-24 Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9 Wiring for the RESET pin .......................................................................................... 3-29 Wiring for clock I/O pins ............................................................................................ 3-30 Wiring for the VPP pin of the One Time PROM and the EPROM version ........ 3-30 Bypass capacitor across the VSS line and the VCC line ...................................... 3-30 Analog signal line and a resistor and a capacitor ................................................ 3-31 Wiring for a large current signal line ...................................................................... 3-31 Wiring to a signal line where potential levels change frequently........................ 3-31 Setup for I/O ports ..................................................................................................... 3-32 Watchdog timer by software ...................................................................................... 3-32
3.5.1 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 7, 8) ......................................................... 3-34 3.5.2 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 7, 8) .......................... 3-34 3.5.3 Structure of Port P6 ................................................................................................... 3-35 3.5.4 Structure of Port P6 direction register .................................................................... 3-35 3.5.5 Structure of Timer XY control register .................................................................... 3-36 3.5.6 Structure of Port P2P3 control register .................................................................. 3-36 3.5.7 Structure of Pull-up control register ........................................................................ 3-37 3.5.8 Structure of Watchdog timer control register ......................................................... 3-37 3.5.9 Structure of Transmit/Receive buffer register ........................................................ 3-38 3.5.10 Structure of Serial I/O1 status register ................................................................. 3-38 3.5.11 Structure of Serial I/O1 control register ............................................................... 3-39 3.5.12 Structure of UART control register ........................................................................ 3-39 3.5.13 Structure of Baud rate generator............................................................................ 3-40 3.5.14 Structure of Serial I/O2 control register 1 ............................................................ 3-40 3.5.15 Structure of Serial I/O2 control register 2 ............................................................ 3-41 3.5.16 Structure of Serial I/O2 register .............................................................................3-41 3.5.17 Structure of Timer X Low-order, Timer X High-order, Timer Y Low-order, Timer Y High-order 3-42
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List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.5.18 3.5.19 3.5.20 3.5.21 3.5.22 3.5.23 3.5.24 3.5.25 3.5.26 3.5.27 3.5.28 3.5.29 3.5.30 3.5.31 3.5.32 3.5.33 3.5.34 3.5.35 3.5.35 3.5.36 3.5.36 Structure of Timer 1, Timer 3 .................................................................................3-42 Structure of Timer 2 ................................................................................................. 3-43 Structure of Timer X mode register ...................................................................... 3-44 Structure of Timer Y mode register ...................................................................... 3-44 Structure of Timer 123 mode register ................................................................... 3-46 Structure of Real time port register ...................................................................... 3-46 Structure of Real time port control register 0 ...................................................... 3-47 Structure of Real time port control register 1 ...................................................... 3-48 Structure of Real time port control register 2 ...................................................... 3-49 Structure of Real time port control register 3 ...................................................... 3-50 Structure of Timer A Low-order, Timer A High-order, Timer B Low-order, Timer B High-order 3-50 Structure of D-A control register ............................................................................3-51 Structure of A-D control register ............................................................................3-51 Structure of A-D conversion register..................................................................... 3-52 Structure of D-Ai conversion register (i = 1,2,3,4) .............................................. 3-52 Structure of Interrupt edge selection register ...................................................... 3-53 Structure of CPU mode register .............................................................................3-53 Structure of Interrupt request register 1 ............................................................... 3-54 Structure of Interrupt request register 2 ............................................................... 3-54 Structure of Interrupt control register 1 ................................................................ 3-55 Structure of Interrupt control register 2 ................................................................ 3-55
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List of tables
List of tables
CHAPTER 1 HARDWARE
Table Table Table Table Table Table Table Table Table Table Table Table 1 Pin description (1)............................................................................................................ 1-4 2 Pin description (2)............................................................................................................ 1-5 3 List of supported products .............................................................................................. 1-7 4 Push and pop instructions of accumulator or processor status register ................. 1-9 5 Set and clear instructions of each bit of processor status register ....................... 1-10 6 List of I/O port functions (1) ......................................................................................... 1-15 7 List of I/O port functions (2) ......................................................................................... 1-16 8 Interrupt vector addresses and priority ...................................................................... 1-21 9 Port functions in memory expansion mode and microprocessor mode ................. 1-57 10 Special programming adapter ..................................................................................... 1-61 11 Interrupt sources, vector addresses and interrupt priority ..................................... 1-62 12 Change of A-D conversion register during A-D conversion .................................. 1-64
CHAPTER 2 APPLICATION
Table 2.1.1 Handling of unused pins (in single-chip mode) .................................................... 2-5 Table 2.1.2 Handling of unused pins (in memory expansion mode and microprocessor mode) ......... 2-5 Table 2.2.1 Function of CNTR0/CNTR1 edge switch bit ........................................................ 2-10 Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values ...................... 2-57
CHAPTER 3 APPENDIX
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 3.1.1 Absolute maximum ratings ....................................................................................... 3-2 3.1.2 Recommended operating conditions (1) ................................................................. 3-3 3.1.3 Recommended operating conditions (2) ................................................................. 3-3 3.1.4 Recommended operating conditions (3) ................................................................. 3-4 3.1.5 Electrical characteristics (1) ..................................................................................... 3-5 3.1.6 Electrical characteristics (2) ..................................................................................... 3-6 3.1.7 A-D converter characteristics ................................................................................... 3-7 3.1.8 D-A converter characteristics ................................................................................... 3-7 3.1.9 Analog comparator characteristics ........................................................................... 3-7 3.1.10 Timing requirements (1) .......................................................................................... 3-8 3.1.11 Timing requirements (2) .......................................................................................... 3-8 3.1.12 Switching characteristics (1)................................................................................... 3-9 3.1.13 Switching characteristics (2)................................................................................... 3-9 3.1.14 Timing requirements in memory expansion mode and microprocessor mode .......................... 3-10 3.1.15 Switching characteristics in memory expansion mode and microprocessor mode ................... 3-10
Table 3.3.1 Programming adapter .............................................................................................. 3-28 Table 3.3.2 Setting of programming adapter switch ............................................................... 3-28 Table 3.3.3 Setting of PROM programmer address ................................................................ 3-28 Table 3.5.1 Function of CNTR0/CNTR1 edge switch bit ........................................................ 3-45
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CHAPTER 1 HARDWARE
DESCRIPTION FEATURES APPLICATIONS PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD FUNCTIONAL DESCRIPTION SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES/APPLICATIONS/PIN CONFIGURATION
DESCRIPTION
The 3807 group is a 8-bit microcomputer based on the 740 family core technology. The 3807 group has two serial I/Os, an A-D converter, a D-A converter, a real time output port function, a watchdog timer, and an analog comparator, which are available for a system controller which controls motors of office equipment and household appliances. The various microcomputers in the 3807 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3807 group, refer to the section on group expansion.
* * * * * * *
*
FEATURES
* * * * * * * * * *
Basic machine-language instructions ....................................... 71 The minimum instruction execution time ............................ 0.5 s (at 8 MHz oscillation frequency) Memory size ................................................................................. ROM .................................................8 to 60 K bytes RAM ............................................ 384 to 2048 bytes Programmable input/output ports ............................................. 68 Software pull-up resistors (Ports P0 to P2) .............................. 24 Input ports (Ports P63 and P64) .................................................. 2 Interrupts .................................................. 20 sources, 16 vectors Timers X, Y ................................................................... 16-bit ! 2 Timers A, B (for real time output port function) ............ 16-bit ! 2 Timers 1-3 ...................................................................... 8-bit ! 3
*
* *
Serial I/O1 (UART or Clock-synchronized) ..................... 8-bit ! 1 Serial I/O2 (Clock-synchronized) .................................... 8-bit ! 1 A-D converter ................................................ 8-bit ! 13 channels D-A converter .................................................. 8-bit ! 4 channels Watchdog timer ............................................................. 16-bit ! 1 Analog comparator ....................................................... 1 channel 2 Clock generating circuit Main clock (XIN-XOUT) ......................... Internal feedback resistor Sub-clock (XCIN-XCOUT) ......... Without internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator) Power source voltage In high-speed mode ................................................... 4.0 to 5.5 V (at 8 MHz oscillation frequency and high-speed selected) In middle-speed mode ............................................... 2.7 to 5.5 V (at 8 MHz oscillation frequency and middle-speed selected) In low-speed mode .................................................... 2.7 to 5.5 V (at 32 kHz oscillation frequency and low-speed selected) Power dissipation In high-speed mode ......................................................... 34 m W (at 8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ............................................................ 60 W (at 32 kHz oscillation frequency, at 3 V power source voltage) Memory expansion ......................................................... possible Operating temperature range ................................... -20 to 85 C
APPLICATION
LBP engine control, PPC, FAX, office equipment, household appliances, consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
P30/RTP6 P31/RTP7 P32/ONW P33/RESETOUT P34/CKOUT/ P35/SYNC P36/WR P37/RD P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13 P16/AD14 P17/AD15
55 60 59 61 56 57 58 62 63 64 53 52 51 50 49 48 47 46 45 44 43 42
P87/RTP5 P86/RTP4 P85/RTP3 P84/RTP2 P83/RTP1 P82/RTP0 P81/DA4/AN12 P80/DA3/AN11 VCC ADVREF AVSS P65/DAVREF/AN10 P64/CMPREF /AN9 P63/CMPIN /AN8 CMPOUT CMPVCC
54
41
40 39 38 37 36 35 34 33
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
M38073M4-XXXFP
32 31 30 29 28 27 26 25
P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 VSS XOUT XIN P40/XCOUT P41/XCIN RESET CNVSS P42/INT0
11 12
13 14 15 16 17 18 19 20
Fig. 1. Pin configuration of M38073M4-XXXFP
1-2
P62/AN7 P61/AN6 P60/AN5 P77/AN4 P76/AN3 P75/AN2 P74/AN1 P73/SRDY2/ADT/AN0 P72/SCLK2 P71/SOUT2 P70/SIN2 P57/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/INT4 P52/INT3 P51/SCMP2/INT2 P50/TOUT P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT1
Package type : 80P6N-A 80-pin plastic-molded QFP
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21 22 23 24
1 2 3 4
5 6 7 8 9
FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N)
Main clock Main clock input output Reset input V
SS CC 27 26 73 32
X IN
X OUT
V
RESET
CNVSS
30
31
FUNCTIONAL BLOCK
Sub-clock Sub-clock output input
Fig. 2. Functional block diagram
CPU
XCIN
XCOUT
Clock generating circuit
RAM ROM
X Timer 1 (8) Y Timer X (16) S
CNTR0 INT0 CNTR1 INT1 CMPIN CMPREF
A
Timer 3 (8) Timer 2 (8)
TOUT
CMPVCC
80
CMPOUT
79
Analog comparator PS
PC H
PCL
Timer Y (16)
Timer A (16) Timer B (16)
3807 GROUP USER'S MANUAL
A-D converter SCMP2
D-A
D-A
SI/O2(8)
(8) D-A converter 2 (8) D-A converter 1 (8)
SI/O1(8)
RTP
converter 4 converter 3
RTP0 - INT2 - INT4
(8)
(8)
RTP5
SCMP2 INT0, XCIN INT1 XCOUT RTP0 - INT4 RTP5
P8(8)
CMPREF DAVREF CMPIN
P7(8)
P6(8)
P5(8)
TOUT
P4(8)
P3(8)
P2(8)
P1(8)
P0(8)
65 66 67 68 69 70 71 72
4 5 6 7 8 9 10 11 76 77 78 123
74 75
12 13 14 15 16 17 18 19
20 21 22 23 24 25 28 29
57 58 59 60 61 62 63 64
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
49 50 51 52 53 54 55 56
I/O port P 8 I/O port P 6
ADVREF AVSS
HARDWARE
I/O port P 7
I/O port P 5
I/O port P 4
I/O port P 3
I/O port P 2
I/O port P 1
I/O port P 0
FUNCTIONAL BLOCK
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HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table. 1. Pin description (1) Pin VCC, VSS CMPVCC CNVSS Name Function Function except a port function
Power source * Apply voltage of 2.7-5.5 V to VCC, and 0 V to VSS. Analog comparator * Power source input pin for an analog comparator power source CNVSS * This pin controls the operation mode of the chip. * Normally connected to VSS. * If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed. * Reference voltage input pin for A-D converter.
ADVREF AVSS CMPOUT
______
Analog reference voltage
Analog power * Analog power source input pin for A-D and D-A converter and an analog comparator source * Connect to VSS. Analog comparator * Output pin for an analog comparator output Reset input Clock input Clock output I/O port P0 I/O port P1 I/O port P2 * Reset input pin for active "L" * Input and output signals for the internal clock generating circuit. * Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. * If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. * The clock is used as the oscillating source of system clock. * 8-bit CMOS I/O port * I/O direction register allows each pin to be individually programmed as either input or output. * At reset this port is set to input mode. * In modes other than single-chip, these pins are used as address, data bus I/O pins. * CMOS compatible input level * CMOS 3-state output structure * Port P2 can be switched CMOS or TTL input level.
RESET XIN XOUT P00-P07 P10-P17 P20-P27
P30/RTP6, I/O port P3 P31/RTP7 P34/CKOUT, P32, P33, P35-P37
* 8-bit CMOS I/O port * Real time port function * I/O direction register allows each pin to be individually programmed as either input or output. pins * At reset this port is set to input mode. * Clock output function pin * In modes other than single-chip, these pins are used as control bus I/O pins. * CMOS compatible input level * CMOS 3-state output structure * Port P32 can be switched CMOS or TTL input level. * 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structures
P40/XCOUT, P41/XCIN P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 P50/TOUT P51/SCMP2/ INT2 P52/INT3, P53/INT4 P54/CNTR0, P55/CNTR1 P56/DA1, P57/DA2
I/O port P4
* Sub-clock generating I/O pins(connect a resonator) * Interrupt input pins * Timer X, Timer Y function pins (INT0, INT1) * Serial I/O1 function pins
I/O port P5
* 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure
* Timer 2 output pin * Interrupt input pin * Serial I/O2 function pin * Interrupt input pin * Real time port function pin(INT4) * Timer X, Timer Y function pins * D-A conversion output pins
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PIN DESCRIPTION
Table. 2. Pin description (2) Pin P60/AN5- P62/AN7 Name I/O port P6 Function * 3-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure P63/CMPIN/ Input port P6 AN8 P64/CMPREF/ AN9 P65/DAVREF/ I/O port P6 AN10 P70/SIN2, P71/SOUT2, P72/SCLK2 P73/SRDY2/ ADT/AN0 P74/AN1- P77/AN4 P80/DA3/ AN11, P81/DA4/ AN12, P82/RTP0- P87/RTP5 * Realtime port function pins I/O port P7 * 2-bit CMOS input port * CMOS compatible input level * Analog comparator input pin * A-D conversion input pin * Reference voltage input pin for analog comparator * A-D conversion input pin * D-A conversion power source input pin * A-D conversion input pin * Serial I/O2 function pins Function except a port function * A-D conversion output pins
* 1-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure * 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structures
* Serial I/O2 function pin * A-D conversion input pin * A-D trigger input pin * A-D conversion input pin I/O port P8 * 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structures * D-A conversion output pin * A-D conversion input pin
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HARDWARE
PART NUMBERING
PART NUMBERING
Product M3807 3 M 4 - XXX FP Package type FP : 80P6N-A package FS : 80D0 package ROM number Omitted in some types. ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes
Fig. 3. Part numbering
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HARDWARE
GROUP EXPANSION
GROUP EXPANSION
Mitsubishi plans to expand the 3807 group as follows:
Memory Type
Support for Mask ROM, One Time PROM and EPROM versions.
Memory Size
ROM/PROM size .................................................... 8K to 60K bytes RAM size ............................................................. 384 to 2048 bytes
Package
80P6N-A ..................................... 0.8 mm-pitch plastic molded QFP 80D0 ........................ 0.8 mm-pitch ceramic LCC (EPROM version)
ROM size (byte) External ROM 60K
Being planned M38078S Under development M38079EF Being planned
48K
Being planned
M38078MC
32K 28K 24K 20K 16K 12K 8K
Mass product Mass product M38073M4 M38073E4
M38077M8
384
512
640
768
896
1024
1152
1280
1408
1536
2048
3072
4032
RAM size (byte) Note : Products under development or planning : the development schedule and specifications may be revised without notice.
Fig. 4. Memory expansion plan Currently supported products are listed below. Table 3. List of supported products Product M38073M4-XXXFP M38073E4-XXXFP M38073E4FP M38073E4FS (P) ROM size (bytes) ROM size for User () 16384 (16254) 80D0 RAM size (bytes) Package Remarks Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version As of May 1996
512
80P6N-A
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HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
The 3807 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 Users Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instructions cannot be used. The MUL, DIV, WIT and STP instruction can be used. The central processing unit (CPU) has the six registers.
Stack pointer (S)
The stack pointer is an 8-bit register used during sub-routine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is "0", then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is "1", then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing register contents onto the stack and popping them from the stack are shown in Fig.6.
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In the index addressing modes, the value of the OPERAND is added to the contents of register X or register Y and specifies the real address. When the T flag in the processor status register is set to "1", the value contained in index register X becomes the address for the second OPERAND.
Program counter (PC)
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
b7
b0
A
b7 b0
Accumulator Index Register X
b0
X
b7
Y
b7 b0
Index Register Y Stack Pointer
b0
S
b15 b7
PCH
b7
PCL
b0
Program Counter
N V T B D I Z C Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag
Fig. 5. 740 Family CPU register structure
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HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt request (Note 1) Execute JSR M (S) Store Return Address on Stack (Note 2) (S) M (S) (S) (PCH) (S - 1) (PCL) (S - 1)
M (S) (S) M (S) (S) M (S) (S)
(PCH) (S - 1) (PCL) (S - 1) (PS) (S - 1) Store Contents of Processor Status Register on Stack Store Return Address on Stack (Note 2)
Subroutine Execute RTS Restore Return Address (S) (PCL) (S) (PCH) (S + 1) M (S) (S + 1) M (S)
Interrupt Service Routine
Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S + 1) M (S) (S + 1) M (S) (S + 1) M (S)
I Flag "0" to "1" Fetch the Jump Vector
Restore Contents of Processor Status Register
Restore Return Address
Note 1 : The condition to enable the interrupt
Interrupt enable bit is "1" Interrupt disable flag is "0" 2 : When an interrupt occurs, the address of the next instruction to be executed is stored in the stack area. When a subroutine is called, the address one before the next instruction to be executed is stored in the stack area.
Fig. 6. Register push and pop at interrupt generation and subroutine call
Table. 4. Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP
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HARDWARE
FUNCTIONAL DESCRIPTION
Processor status register (PS)
The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to "1", but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. (2) Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". (3) Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". When an interrupt occurs, this flag is automatically set to "1" to prevent other interrupts from interfering until the current interrupt is serviced. (4) Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. (5) Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". The saved processor status is the only place where the break flag is ever set. (6) Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal addressing modes. (7) Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. (8) Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag.
Table. 5. Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag _ _ I flag SEI CLI D flag SED CLD B flag _ _ T flag SET CLT V flag _ CLV N flag _ _
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FUNCTIONAL DESCRIPTION
CPU Mode Register
The CPU mode register contains the stack page selection bit and processor mode bits. The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not available Stack page selection bit 0 : 0 page 1 : 1 page XCOUT drivability selection bit 0 : Low drive 1 : High drive Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0 : oscillating 1 : stopped Main clock division ratio selection bits b7 b6 0 0 : = f(XIN)/2 (high-speed mode) 0 1 : = f(XIN)/8 (middle-speed mode) 1 0 : = f(XCIN)/2 (low-speed mode) 1 1 : Not available
Fig. 7. Structure of CPU mode register
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Memory Special function register (SFR) area
The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
Special page ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the reset is user area for storing programs. The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM capacity (byte) Address XXXX16
000016 SFR area 004016 RAM 010016 Zero page
192 256 384 512 640 768 896 1024 1536 2048 ROM area
ROM capacity (byte)
00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16
XXXX16 Reserved area 084016 Not used
Address YYYY16
Address ZZZZ16
4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440
F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016
F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016
ROM
YYYY16 Reserved ROM area
(128 byte)
ZZZZ16
FF0016
FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area
Special page
Fig. 8. Memory map diagram
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Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D) Timer X (low-order) (TXL) Timer X (high-order) (TXH) Timer Y (low-order) (TYL) Timer Y (high-order) (TYH) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer X mode register (TXM) Timer Y mode register (TYM) Timer 123 mode register (T123M) Real time port register (RTP) Real time port control register 0 (RTPCON0) Real time port control register 1 (RTPCON1) Real time port control register 2 (RTPCON2) Real time port control register 3 (RTPCON3) Timer A (low-order) (TAL) Timer A (high-order) (TAH) Timer B (low-order) (TBL) Timer B (high-order) (TBH) D-A control register (DACON) A-D control register (ADCON) A-D conversion register (AD) D-A1 conversion register (DA1) D-A2 conversion register (DA2) D-A3 conversion register (DA3) D-A4 conversion register (DA4)
Interrupt edge selection register (INTEDGE)
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316
Timer XY control register (TXYCON) Port P2P3 control register (P2P3C) Pull-up control register (PULL) Watchdog timer control register (WDTCON) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register 1 (SIO2CON1) Serial I/O2 control register 2 (SIO2CON2) Serial I/O2 register (SIO2)
003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Interrupt control register 2(ICON2)
Fig. 9. Memory map of special function register (SFR)
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I/O Ports
[Direction Registers] PiD The 3807 group has 68 programmable I/O pins arranged in nine individual I/O ports (P0--P5, P60--P62, P65 and P7--P8). The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that pin, that pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input (the bit corresponding to that pin must be set to "0") are floating and the value of that pin can be written to. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. [Pull-up Control Register] PULL Ports P0, P1 and P2 have built-in programmable pull-up resistors. The pull-up resistors are valid only in the case that the each control bit is set to "1" and the corresponding port direction registers are set to input mode. (1) CMOS/TTL input level selection Either CMOS input level or TTL input level can be selected as an input level for ports P20 to P27 and P32. The input level is selected by P2*P32 input level selection bit (b7) of the port P2P3 control register (address 001516). When the bit is set to "0", CMOS input level is selected. When the bit is set to "1", the TTL input level is selected. After this bit is re-set, its initial value depends on the state of the CNVss pin. When the CNVss pin is connected to Vss, the initial value becomes "0". When the CNVss pin is connected to Vcc, the initial value becomes "1". (2) Notes on STP instruction execution Make sure that the input level at each pin is either 0V or to Vcc during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.
b7 b0 Port P2P3 control register (P2P3C : address 001516) P34 Clock output control bit 0: I/O port 1: Clock output Output clock frequency selection bit 000: 001: f(XCIN) 010: "L" fixed output 011: "L" fixed output (f(XCIN) in low-speed mode) 100: f(XIN) 101: f(XIN)/2 (f(XCIN)/2 in low-speed mode) 110: f(XIN)/4 (f(XCIN)/4 in low-speed mode) 111: f(XIN)/16 (f(XCIN)/16 in low-speed mode) Not used (return "0" when read) P2 * P32 input level selection bit 0: CMOS level input 1: TTL level input
Fig. 10. Structure of Port P2P3 control register
b7
b0 Pull-up control register (PULL : address 001616) P00--P03 pull-up control bit P04,P05 pull-up control bit P06 pull-up control bit P07 pull-up control bit P10--P13 pull-up control bit P14--P17 pull-up control bit P20--P23 pull-up control bit P24--P27 pull-up control bit 0: No pull-up 1: Pull-up
Fig. 11. Structure of Pull-up control register
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Table. 6. List of I/O port functions (1) Pin P00-P07 P10-P17 P20-P27 Name Port P0 Port P1 Port P2 Input/Output Input/output, individual bits I/O Format CMOS 3-state output CMOS/TTL input level CMOS 3-state output Non-Port Function Related SFRs CPU mode register Ref.No. (1)
CMOS compatible input level Address low-order byte output
P30/RTP6, P31/RTP7 P32 P33 P34/CKOUT P35-P37
Port P3
Address high-order byte output Pull-up control register Data bus I/O CPU mode register Pull-up control register Port P2P3 control register CMOS compatible input level Real time port output CPU mode register CMOS 3-state output Real time port control register CMOS/TTL input level Control signal input CMOS 3-state output CMOS compatible input level Control signal output CMOS 3-state output Clock output, output Control signal I/O Sub-clock generating circuit CPU mode register Port P2P3 control register CPU mode register CPU mode register Port P2P3 control register CPU mode register CPU mode register
(2) (3)
(4) (3) (5) (6) (7) (8) (9) (10) (11) (12) (22) (7) (13) (14) (15) (16)
P40/XCOUT, Port P4 P41/XCIN P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 P50/TOUT P51/SCMP2/ INT2
External interrupt input Interrupt edge selection register Timer X, Timer Y function input Serial I/O1 function I/O Serial I/O1 control register UART control register
Port P5
Timer 2 output External interrupt input Serial I/O2 function I/O External interrupt input Real time port trigger input (INT4) Timer X, Timer Y function I/O D-A conversion output A-D conversion input Input CMOS compatible input level Analog comparator input pin A-D conversion input Analog comparator reference voltage input pin A-D conversion input CMOS compatible input level D-A converter power source CMOS 3-state output input A-D conversion input Serial I/O2 function I/O
Timer 123 mode register Interrupt edge selection register Serial I/O2 control register Interrupt edge selection register Timer X mode register Timer Y mode register D-A control register A-D control register A-D control register
P52/INT3, P53/INT4 P54/CNTR0 P55/CNTR1 P56/DA1, P57/DA2 P60/AN5-- Port P6 P62/AN7 P63/CMPIN/ AN8 P64/CMPREF/ AN9 P65/DAVREF/ AN10 P70/SIN2, P71/SOUT2, P72/SCLK2 P73/SRDY2/ ADT/AN0 P74/AN1-- P77/AN4 Port P7
Input/output, individual bits
A-D control register
(17)
Serial I/O2 control register
Serial I/O2 function I/O A-D trigger input A-D conversion input A-D conversion input
Serial I/O2 control register A-D control register A-D control register
(18) (19) (20) (21)
(15)
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Table. 7. List of I/O port functions (2) Pin P80/DA3/ AN11 P81/DA4/ AN12 P82/RTP0-- P87/RTP5 Name Port P8 Input/Output Input/output, individual bits I/O Format CMOS 3-state output Non-Port Function A-D conversion input Related SFRs D-A control register A-D control register Ref.No. (14)
CMOS compatible input level D-A conversion output
Real time port output
Real time port control register
(23)
Note1 : For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer to the applicable sections. 2 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.
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(1) Ports P0--P2
Pull-up control
(2) Ports P30,P31
Real time port output selection bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch Data for real time port *1
(3) Ports P32,P33,P35--P37
Direction register
(4) Port P34
Clock output control
Direction register
Data bus
Port latch Data bus Port latch
*1 Clock output
(5) Port P40
Port XC switch bit
Direction register
(6) Port P41
Port XC switch bit
Direction register
Data bus
Port latch
Data bus
Port latch
Oscillator Port P41 Port XC switch bit Sub-clock oscillating circuit input
(7) Ports P42,P43,P52,P53
Direction register
(8) Port P44
Serial I/O1 enable bit Receive enable bit
Direction register
Data bus
Port latch
Data bus
Port latch
Interrupt input Timer X input (P42) Timer Y input (P43) RTP trigger input (P53) except P52 *1 Either CMOS input level or TTL input level can be selected as an input level for ports P20 to P27 and P32 by P2*P32 input level selection bit.
serial I/O1 input
Fig. 12. Port block diagram (1)
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(9) Port P45
P45/TXD P-channel output disable bit Serial I/O1 enable bit Transmit enable bit
Direction register
(10) Port P46
Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1mode selection bit Serial I/O1enable bit
Direction register
Data bus
Port latch Data bus Port latch
Serial I/O1 output Serial I/O1 clock output Serial I/O1 external clock input
(11) Port P47
Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit
Direction register
(12) Port P50
Direction register
Data bus
Port latch
Data bus
Port latch TOUT output control bit Timer 2 output
Serial I/O1 ready output
(13) Ports P54,P55
Direction register
(14) Ports P56,P57,P80,P81
Direction register
Data bus
Port latch Data bus Port latch
Timer X, Timer Y operating mode bits
"001" "100" "101" "110" Timer output CNTR0, CNTR1 interrupt input
D-A conversion output DA1 output enable bit (P56) DA2 output enable bit (P57) DA3 output enable bit (P80) DA4 output enable bit (P81) A-D conversion input Analog input pin selection bit except P56,P57
(15) Ports P60--P62,P74--P77
Direction register
(16) Ports P63,P64
Data bus
Port latch
Data bus
A-D conversion input Analog input pin selection bit A-D conversion input Analog input pin selection bit Analog comparator input
Fig. 13. Port block diagram (2)
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(17) Port P65
Direction register
(18) Port P70
Direction register
Data bus
Port latch
Data bus
Port latch
D-A conversion power source input A-D conversion input Analog input pin selection bit
Serial I/O2 input
(19) Port P71
P71/SOUT2 P-channel output disable bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit
Direction register
(20) Port P72
Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit
Direction register
P72/SCLK2 P-channel output disable bit
Data bus
Port latch
Data bus
Port latch
Serial I/O2 clock output Serial I/O2 clock output Serial I/O2 external clock input
(21) Port P73
SRDY2 output enable bit
Direction register
(22) Port P51
Serial I/O2 I/O comparison signal control bit
Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O2 ready output AD external trigger valid bit A-D trigger interrupt input A-D conversion input Analog input pin selection bit
Serial I/O2 I/O comparison signal output Interrrupt input
(23) Ports P82--P87
Real time port output selection bit
Direction register
Data bus
Port latch
Data for real time port
Fig. 14. Port block diagram (3)
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FUNCTIONAL DESCRIPTION
Interrupts
Interrupts occur by twenty sources: eight external, eleven internal, and one software. (1) Interrupt Control Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occurs at the same time the interrupt with highest priority is accepted first. (2) Interrupt Operation Upon acceptance of an interrupt the following operations are automatically performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status register are automatically pushed onto the stack 3. Concurrently with the push operation, the interrupt jump destination address is read from the vector table into the program counter. 4. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. sNotes on Use When the active edge of an external interrupt (INT0--INT4, CNTR0 or CNTR1) is set or the timer /INT interrupt source and the ADT/ A-D conversion interrupt source are changed, the corresponding interrupt request bit may also be set. Therefore, please take following sequence: (1) Disable the external interrupt which is selected. (2) Change the active edge in interrupt edge selection register (in case of CNTR0: Timer X mode register ; in case of CNTR1: Timer Y mode register). (3) Clear the set interrupt request bit to "0." (4) Enable the external interrupt which is selected.
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Table. 8. Interrupt vector addresses and priority Interrupt Source Priority Reset (Note 2) INT0 INT1 Serial I/O1 receive Serial I/O1 transmit Timer X Timer Y INT3 6 7 8 FFF316 FFF116 FFEF16 FFF216 FFF016 FFEE16 1 2 3 4 5 Vector Addresses (Note 1) High FFFD16 FFFB16 FFF916 FFF716 FFF516 Low FFFC16 FFFA16 FFF816 FFF616 FFF416 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data receive At completion of serial I/O1 data transmit shift or when transmit buffer is empty At timer X underflow At timer Y underflow At detection of either rising or falling edge of INT3 input At timer 2 underflow At detection of either rising or falling edge of INT4 input At timer 3 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At completion of serial I/O2 data transmit and receive At detection of either rising or falling edge of INT2 input At timer 1 underflow At timer A underflow At timer B underflow At completion of A-D conversion At falling edge of ADT input Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected Remarks
External interrupt (active edge selectable) Valid when INT3 interrupt is selected Valid when timer 2 interrupt is selected External interrupt (active edge selectable) Valid when INT4 interrupt is selected Valid when timer 3 interrupt is selected External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O2 is selected External interrupt (active edge selectable) Valid when INT2 interrupt is selected Valid when timer 1 interrupt is selected
Timer 2 INT4
9
FFED16
FFEC16
Timer 3 CNTR0 CNTR1 Serial I/O2 INT2
10 11 12 13
FFEB16 FFE916 FFE716 FFE516
FFEA16 FFE816 FFE616 FFE416
Timer 1 Timer A Timer B A-D conversion ADT
14 15 16
FFE316 FFE116 FFDF16
FFE216 FFE016 FFDE16
Valid when A-D interrupt is selected External interrupt(valid at falling) Valid when ADT interrupt is selected and when A-D external trigger is selected. Non-maskable software interrupt
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Note1 : Vector addresses contain interrupt jump destination addresses. 2 : Reset function in the same way as an interrupt with the highest priority.
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FUNCTIONAL DESCRIPTION
Interrupt request bit Interrupt enable bit
Interrupt disable flag I
BRK instruction Reset
Interrupt request
Fig. 15. Interrupt control
b7
b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit INT4 interrupt edge selection bit Timer 1/INT2 interrupt source bit Timer 2/INT3 interrupt source bit Timer 3/INT4 interrupt source bit
0 : Falling edge active 1 : Rising edge active 0 : INT interrupt selected 1 : Timer interrupt selected b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1 interrupt request bit Serial I/O2 interrupt request bit Timer 1/INT2 interrupt request bit Timer A interrupt request bit Timer B interrupt request bit ADT/AD conversion interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued
b7
b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2/INT3 interrupt request bit Timer 3/INT4 interrupt request bit
b7
b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2/INT3 interrupt enable bit Timer 3/INT4 interrupt enable bit
b7
b0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1 interrupt enable bit Serial I/O2 interrupt enable bit Timer 1/INT2 interrupt enable bit Timer A interrupt enable bit Timer B interrupt enable bit ADT/AD conversion interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit) 0 : Interrupt disabled 1 : Interrupt enabled
Fig. 16. Structure of Interrupt-related registers
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Timers
The 3807 group has seven timers : four 16-bit timers (Timer X, Timer Y, Timer A, and Timer B) and three 8-bit timers (Timer 1, Timer 2, and Timer 3). All timers are down-counters. When the timer reaches either "0016" or "000016", an underflow occurs with the next count pulse. Then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1." Read and write operation on 16-bit timer must be performed for both high- and low-order bytes. When reading a 16-bit timer, read from the high-order byte first. When writing to 16-bit timer, write to the loworder byte first. The 16-bit timer cannot perform the correct operation when reading during write operation, or when writing during read operation. Timers A and B are real time output port timers. For details, refer to the section "Real time output port". qTimer X, Timer Y Timer X and Y are independent 16-bit timers which can select enable seven different operation modes each by the setting of their mode registers. The related registers of timer X and Y are listed below. The following register abbreviations are used: * Timer XY control register (TXYCON: address 001416) * Port P4 direction register (P4D: address 000916) * Port P5 direction register (P5D: address 000B16) * Timer X (low-order) (TXL: address 002016) * Timer X (high-order) (TXH: address 002116) * Timer Y (low-order) (TYL: address 002216) * Timer Y (high-order) (TYH: address 002316) * Timer X mode register (TXM: address 002716) * Timer Y mode register (TYM: address 002816) * Interrupt edge selection register (INTEDGE: address 003A16) * Interrupt request register 1 (IREQ1: address 003C16) * Interrupt request register 2 (IREQ2: address 003D16) * Interrupt control register 1 (ICON1: address 003E16) * Interrupt control register 2 (ICON2: address 003F16) For details, refer to the structures of each register. The following is an explanation of the seven modes: (1) Timer * event counter mode Timer mode * Mode selection This mode can be selected by setting "000" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM * Count source selection In high- or middle-speed mode, f(XIN)/2, f(XIN)/16, or f(XCIN) can be selected as the count source. In low-speed mode the count source is f(XCIN). A count source is selected by the following bit. Timer X count source selection bit (bits 7 and 6) of TXM Timer Y count source selection bit (bits 7 and 6) of TYM * Interrupt When an underflow is generated, the corresponding timer X interrupt request bit (b4) or timer Y interrupt request bit (b5) of IREQ1 is set to "1". * Explanation of operation After reset release, timer X stop control bit (b0) and timer Y stop control bit (b1) of TXYCON are set to "1"and the timer stops. During timer stop, a timer value written to the timer X or timer Y is set by writing data to the corresponding timer latch and timer at the same time. The timer operation is started by setting the bits 0 or 1 of TXYCON to "0". When the timer reaches "000016", an underflow occurs with the next count pulse. Then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. For changing a timer value during count operation, a latch value must be changed by writing data only to the corresponding latch first. Then the timer is reloaded with the new latch value at the next underflow. Event counter mode * Mode selection This mode can be selected by the following sequence. 1. Set "000" to the timer X operating mode bit (bits 2 to 0) of TXM, or to the timer Y operating mode bit (bits 2 to 0) of TYM. 2. Select an input signal from the CNTR0 pin (in case of timer X ; set "11" to bits 7 and 6 of TXM), or from the CNTR1 pin (in case of timer Y ; set "11" to bits 7 and 6 of TYM) as a count source. The valid edge for the count operation is selected by the CNTR0/ CNTR1 active edge switch bit (b5) of TXM or TYM: if set to "0", counting starts with the rising edge or if set to "1", counting starts with the falling edge. * Interrupt The interrupt generation at underflow is the same as already explained for the timer mode. * Explanation of operation The operation is the same as already explained for the timer mode. In this mode, the double-function port of CNTR0/CNTR1 pin must be set to input. Figure 19 shows the timing chart for the timer * event counter mode. (2) Pulse output mode * Mode selection This mode can be selected by setting "001" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM * Count source selection In high- or middle-speed mode, f(XIN)/2, f(XIN)/16, or f(XCIN) can be selected as the count source. In low-speed mode the count source is f(XCIN). * Interrupt The interrupt generation at underflow is the same as already explained for the timer mode. * Explanation of operation Counting operation is the same as in timer mode. Moreover the pulse which is inverted each time the timer underflows is output from CNTR0/CNTR1 pin. When the CNTR0/CNTR1 active edge switch bit (b5) of TXM or TYM is "0", output starts with "H" level. When set to "1", output starts with "L" level.
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sPrecautions Set the double-function port of CNTR0/CNTR1 pin to output in this mode. [During timer operation stop] The output from CNTR0/CNTR1 pin is initialized to the level set through CNTR0/CNTR1 active edge switch bit. [During timer operation enabled] When the value of the CNTR0/CNTR1 active edge switch bit is written over, the output level of CNTR0/CNTR1 pin is inverted. Figure 20 shows the timing chart of the pulse output mode. (3) Pulse period measurement mode * Mode selection This mode can be selected by setting "010" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM * Count source selection In high- or middle-speed mode, f(XIN)/2 or f(XIN)/16 can be selected as the count source. In low-speed mode the count source is f(XCIN). * Interrupt The interrupt generation at underflow is the same as already explained for the timer mode. Bits 0 or 1 of IREQ2 is set to "1" synchronously to pulse period measurement completion. * Explanation of operation [During timer operation stop] Select the count source. Next, select the interval of the pulse periods to be measured. When bit 5 of the TXM or TYM is set to "0", the timer counts during the interval of one falling edge of CNTR0/ CNTR1 pin input until the next falling edge of input. If bits 5 are set to "1", the timer counts during the interval of one rising edge until the next rising edge. [During timer operation enabled] The pulse period measurement starts by setting bit 0 or 1 of TXYCON to "0" and the timer counts down from the value that was set to the timer before the start of measurement. When a valid edge of measurement start/stop is detected, the 1's complement of the timer value is written to the timer latch and "FFFF16" is set to the timer. Furthermore when the timer underflows, a timer X/Y interrupt request occurs and "FFFF16" is set to the timer. The measured value is held until the next measurement completion. sPrecautions Set the double-function port of CNTR0/CNTR1 pin to input in this mode. A read-out of timer value is impossible in this mode. The timer is written to only during timer stop (no measurement of pulse periods). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operations during measurement. The timer is set to "FFFF16" when the timer either underflows or a valid edge of pulse period measurement is detected. Due to that, the timer value at the start of measurement depends on the timer value before the start of measurement. Figure 21 shows the timing chart of the pulse period measurement mode. (4) Pulse width measurement mode * Mode selection This mode can be selected by setting "011" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM * Count source selection In high- or middle-speed mode, f(XIN)/2 or f(XIN)/16 can be selected as the count source. In low-speed mode the count source is f(XCIN). * Interrupt The interrupt generation at underflow is the same as already explained for the timer mode. Bit 0 or 1 of IREQ2 is set to "1" synchronously to pulse width measurement completion. * Explanation of operation [During timer operation stop] Select the count source. Next, select the interval of the pulse widths to be measured. When bit 5 of TXM or TYM is set to "1", the timer counts during the interval of one falling edge of CNTR0/CNTR1 pin input until the next rising edge of input ("L" interval). If bit 5 is set to "0", the timer counts during the interval of one rising edge until the next falling edge ("H" interval). [During timer operation enabled] The pulse width measurement starts by setting bit 0 or 1 of TXYCON to "0" and the timer counts down from the value that was set to the timer before the start of measurement. When a valid edge of measurement completion is detected, the 1's complement of the timer value is written to the timer latch and "FFFF16" is set to the timer. Furthermore when the timer underflows, a timer X/Y interrupt request occurs and "FFFF16" is set to the timer. The measured value is held until the next measurement completion. sPrecautions Set the double-function port of CNTR0/CNTR1 pin to input in this mode. A read-out of timer value is impossible in this mode. The timer is written to only during timer stop (no measurement of pulse widths). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operations during measurement. The timer value is set to "FFFF16" when the timer either underflows or a valid edge of pulse widths measurement is detected. Due to that, the timer value at the start of measurement depends on the timer value before the start of measurement. Figure 22 shows the timing chart of the pulse width measurement mode. (5) Programmable waveform generation mode * Mode selection This mode can be selected by setting "100" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM * Count source selection In high- or middle-speed mode, f(XIN)/2, f(XIN)/16, or f(XCIN) can be selected as the count source. In low-speed mode the count source is f(XCIN). * Interrupt The interrupt generation at underflow is the same as already
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explained for the timer mode. * Explanation of operation Counting operation is the same as in timer mode. Moreover the timer outputs the data set in the corresponding output level latch (bit 4 of TXM or TYM) to CNTR0/CNTR1 pin each time the timer underflows. After the timer underflows, the generation of optional waveform from CNTR0/CNTR1 pin is possible through a change of values in the output level latch and timer latch. sPrecautions Set the double-function port of CNTR0/CNTR1 pin to output in this mode. Figure 23 shows the timing chart of the programmable waveform generation mode. (6) Programmable one-shot generating mode * Mode selection This mode can be selected by setting "101" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM * Count source selection In high- or middle-speed mode, f(XIN)/2 or f(XIN)/16 can be selected as the count source. * Interrupt The interrupt generation at underflow is the same as already explained for the timer mode. The one-shot generating trigger condition must be set to the INT0 interrupt edge selection bit (b0) and INT1 interrupt edge selection bit (b1) of INTEDGE. Setting these bits to "0" causes the interrupt request being triggered by a falling edge, setting them to "1" causes the interrupt request being triggered by a rising edge. The INT0 interrupt request bit (b0) and INT1 interrupt request bit (b1) of IREQ1 are set to "1" by detecting the active edge of the INT pin. * Explanation of operation For a "H" one-shot pulse, set bit 5 of TXM, TYM to "0". [During timer operation stop] The output level of CNTR0/CNTR1 pin is initialized to "L" at mode selection. Set the one-shot pulse width to TXH, TXL, TYH, TYL. A trigger generation during timer stop (input signal to INT0/INT1 pin) is invalid. [During timer operation enabled] When a trigger generation is detected, "H" is output, and at underflow "L" is output from CNTR0/CNTR1 pin. For a "L" one-shot pulse set bit 5 of TXM, TYM to "1". [During timer operation stop] The output level of CNTR0/CNTR1 pin is initialized to "H" at mode selection. Set the one-shot pulse width to TXH, TXL, TYH, TYL. A trigger generation during timer stop (input signal to INT0/INT1 pin) is invalid. [During timer operation enabled] When a trigger generation is detected, "L" is output, and at underflow "H" is output from CNTR0/CNTR1 pin. sPrecautions * Set the double-function port of CNTR0/CNTR1 pin to output and the double-function port of INT0/INT1 pin to input in this mode. * This mode is unused in low-speed mode. * During one-shot generation permission or one-shot generation the output level from CNTR0/CNTR1 pin changes if the value of the CNTR0/CNTR1 active edge switch bit is inverted. Figure 24 shows the timing chart of the programmable one-shot generating mode. (7) PWM mode * Mode selection This mode can be selected by setting "110" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM * Count source selection In high- or middle-speed mode, f(XIN)/2 or f(XIN)/16 can be selected as the count source. * Interrupt With a rising edge of CNTR0/CNTR1 output, the timer X interrupt request bit (b4) and timer Y interrupt request bit (b5) of IREQ1 are set to "1". * Explanation of operation PWM waveform is output from CNTR0 pin (in case of timer X) or from CNTR1 pin (in case of timer Y). The "H" interval of PWM waveform is determined by the setting value m (m=0 to 255) of TXH and TYH and the "L" interval of PWM waveform is determined by the setting value n (n=0 to 255) of TXL and TYL. The PWM cycles are: PWM cycle time = (m+n)*ts PWM duty = m/(m+n) where: ts: period of timer X/timer Y count source [During count operation stop] When a timer value is set to TXL, TXH, TYL, TYH by writing data to timer and timer latch at the same time. When setting this value, the output of CNTR0/CNTR1 pin is initialized to the "H" level. [During count operation enabled] By setting the bit 0 or 1 of TXYCON to "0", an "H" interval of TXH or TYH is output first, and after that a "L" level interval of TXL or TYL are output next. These operations are repeated continuously. The PWM output is changed after the underflow by setting a timer value, which is set by writing data to the timer latch only, to TXL, TXH, TYL, TYH. sPrecautions * Set the double-function port of CNTR0/CNTR1 pin to output in this mode. * This mode is unused in low-speed mode. * When the PWM "H" interval is set to "0016", PWM output is "L". * When the PWM "L" interval is set to "0016", PWM output is "H". * When the PWM "H" interval and "L" interval are set to "0016", PWM output is "L". * When a PWM "H" interval or "L" interval is set to "0016" at least for a short time, timer X/timer Y interrupt request does not occur. * When the value set to the timer latch is "0016", the value is undefined since the timer counts down by dummy count operation. Figure 25 shows the timing chart of the PWM mode.
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sPrecautions regarding all modes * Timer X, timer Y writing control One of the following operation is selected by bit 3 of TXM or TYM for timer X or timer Y. Writing data to the corresponding latch and timer at the same time Writing data to only corresponding latch When the operation "writing data to only corresponding latch" is selected, the value is set to the timer latch by writing a value to timer X/Y address and a timer is renewed at the next underflow. After releasing a reset, "writing the corresponding latch and timer at the same time" is selected. When a value is written to timer X/Y address, a value is set to a timer and a timer latch at the same time. When "writing data to only corresponding latch" is selected, if writing to a reload latch and an underflow are performed at the same timing, the timer value is undefined. * Timer X, timer Y read control In pulse period measurement mode and pulse width measurement mode the timer value cannot be read-out. In all other modes readout operations without effect to count operations/stops are possible. However, the timer latch value cannot be read-out. * Precautions regarding the CNTR0/CNTR1 active edge switch bit and the INT0/INT1 interrupt edge selection bit: The CNTR0/CNTR1 active edge switch bit and the INT0/INT1 interrupt edge selection bit settings have an effect also on each interrupt active edge.
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CNTR0 active edge switch bit Programmable one-shot "1" P42/INT0 Programmable one-shot generating mode PWM mode PWM mode PWM generating circuit Programmable one-shot generating circuit "0" generating mode
Data bus
INT0 interrupt request Programmable waveform generating mode Output level latch D T pulse output mode S Q T "001" "100" "101" "110" Timer X operating mode bits Timer X latch (low-order) P54 latch Timer X (low-order) Q CNTR0 active edge switch bit "0" "1" Pulse output mode Q
Timer X latch (high-order) Timer X (high-order) Timer X interrupt request
P54 direction register
Pulse period measurement mode Pulse width measurement mode
Edge detection circuit
CNTR0 interrupt request "1" P54/CNTR0 f(XIN)/2 f(XIN)/16 f(XCIN)
"0" CNTR0 active edge switch bit
Timer X stop control bit Timer X count source selection bits
P43/INT1 Programmable one-shot generating mode
CNTR1 active edge switch bit Programmable one-shot "1" generating mode Programmable one-shot generating circuit "0" PWM mode PWM mode PWM generating circuit INT1 interrupt request Programmable waveform generating mode Output level latch D T Q Pulse output mode CNTR1 active edge switch bit "0" "1" Pulse output mode
S Q T "001" "100" "101" "110" Timer Y operating mode bits P55 latch P55 direction register Timer Y latch (low-order) Timer Y (low-order) Q
Timer Y latch (high-order) Timer Y (high-order) Timer Y interrupt request
Pulse period measurement mode Pulse width measurement mode
Edge detection circuit
CNTR1 interrupt request "1" P55/CNTR1 f(XIN)/2 f(XIN)/16 f(XCIN)
"0" CNTR1 active edge switch bit
Timer Y stop control bit Timer Y count source selection bits
Fig. 17. Block diagram of Timer X and Timer Y
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b7
b0
b7
b0
Timer X mode register (TXM : address 002716) Timer X operating mode bits b2 b1 b0 0 0 0 : Timer * event counter mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generating mode 1 0 1 : Programmable one-shot generating mode 1 1 0 : PWM mode 1 1 1 : Not used Timer X write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Output level latch 0 : "L" output 1 : "H" output CNTR0 active edge switch bit 0 : * Event counter mode ; counts rising edges * Pulse output mode ; output starts with "H" level * Pulse period measurement mode ; measures between two falling edges * Pulse width measurement mode ; measures "H" periodes * Programmable one-shot generating mode ; after start at "L" level, output a "H" pulse (interrupt request is triggered on falling edge) 1 : * Eevent counter mode ; counts falling edges * Pulse output mode ; output starts with "L" level * Pulse period measurement mode ; measures between two rising edges * Pulse width measurement mode ; measures "L" periodes * Programmable one-shot generating mode ; after start at "H" level, output a "L" pulse (interrupt request is triggered on rising edge) Timer X count source selection bits b7 b6 0 0 : f(XIN)/2 0 1 : f(XIN)/16 1 0 : f(XCIN) 1 1 : Input signal from CNTR0 pin
Timer Y mode register (TYM : address 002816) Timer Y operating mode bits b2 b1 b0 0 0 0 : Timer*event counter mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generating mode 1 0 1 : Programmable one-shot generating mode 1 1 0 : PWM mode 1 1 1 : Not used Timer Y write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Output level latch 0 : "L" output 1 : "H" output CNTR1 active edge switch bit 0 : * Event counter mode ; counts rising edges * Pulse output mode ; output starts with "H" level * Pulse period measurement mode ; measures between two falling edges * Pulse width measurement mode ; measures "H" periodes * Programmable one-shot generating mode ; after start at "L" level, output a "H" pulse (interrupt request is triggered on falling edge) 1 : * Eevent counter mode ; counts falling edges * Pulse output mode ; output starts with "L" level * Pulse period measurement mode ; measures between two rising edges * Pulse width measurement mode ; measures "L" periodes * Programmable one-shot generating mode ; after start at "H" level, output a "L" pulse (interrupt request is triggered on rising edge) Timer Y count source selection bits b7 b6 0 0 : f(XIN)/2 0 1 : f(XIN)/16 1 0 : f(XCIN) 1 1 : Input signal from CNTR1 pin
b7
b0
Timer XY control register (TXYCON : address 001416)
Timer X stop control bit 0 : start counting 1 : stop counting Timer Y stop control bit 0 : start counting 1 : stop counting Not used (returns "0" when read)
Fig. 18. Structure of Timer X mode register, Timer Y mode register, and Timer XY control register
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FFFF16 TL
000016 TR TR TR
TL: A value set to a timer latch TR: Timer interrupt request
Fig. 19. Timing chart of Timer*Event counter mode
FFFF16
TL
000016 TR TR TR TR
Waveform output from CNTR0/CNTR1 pin
CNTR
CNTR
TL: A value set to a timer latch TR: Timer interrupt request CNTR: CNTR0/CNTR1 interrupt request This example's condition: CNTR0/CNTR1 active edge switch bit "0": output starts with "H" level, interrupt at falling edge
Fig. 20. Timing chart of Pulse output mode
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000016 T3 T2 T1 FFFF16 TR FFFF16+T1 T2 T3 FFFF16 TR
Signal input from CNTR0/CNTR1 pin CNTR CNTR CNTR CNTR TR: Timer interrupt request CNTR: CNTR0/CNTR1 interrupt request This example's condition: CNTR0/CNTR1 active edge switch bit set to "1" measure from rising edge to rising edge; interrupt at rising edge
Fig. 21. Timing chart of Pulse period measurement mode
000016 T3 T2 T1 FFFF16 TR TR
FFFF16+T2 Signal input from CNTR0/CNTR1 pin CNTR TR: Timer interrupt request CNTR: CNTR0/CNTR1 interrupt request This example's condition: CNTR0/CNTR1 active edge switch bit set to "1" measure "L" width; interrupt at rising edge
Fig. 22. Timing chart of Pulse width measurement mode
T3
T1
CNTR
CNTR
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FFFF16 T3 L T2 T1 000016
Signal output from CNTR0/CNTR1 pin
L TR
T1
T3
T2
TR TR TR CNTR CNTR L: Initial value of timer TR: Timer interrupt request CNTR: CNTR0/CNTR1 interrupt request
This example's condition: CNTR0/CNTR1 active edge switch bit set to "0" output starts with "L" level; interrupt at falling edge
Fig. 23. Timing chart of Programmable waveform generating mode
FFFF16
L
TR Signal input from INT0/INT1 pin Signal output from CNTR0/CNTR1 pin
TR
TR
L CNTR
L CNTR
L
L: One-shot pulse width; timer latch value TR: timer interrupt request CNTR: CNTR0/CNTR1 interrupt request This example's condition: CNTR0/CNTR1 active edge switch bit set to "0" output a "H" pulse; interrupt at falling edge
Fig. 24. Timing chart of Programmable one-shot generating mode
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ts Timer X/Timer Y count source
Timer X/Timer Y PWM output signal m ! ts n ! ts (m+n) ! ts CNTR TR CNTR: CNTR0/CNTR1 interrupt request TR: Timer interrupt request PWM waveform (duty : m/(m + n) and period: (m + n) ! ts) is output m : the setting value of TXH/TYH (m = 0 to 255) n: the setting value of TXL/TYL (n = 0 to 255) ts: the period of timer X / timer Y count source TR
This example's condition: CNTR0/CNTR1 active edge switch bit set to "0" output starts with "H" level; interrupt at falling edge
Fig. 25. Timing chart of PWM mode
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qTimer 1, Timer 2, Timer 3
Timer 1 to 3 are 8-bit timers for which the count source can be selected through timer 123 mode register.
b7 b0
(1) Timer 2 write control Timer 2 write control bit (b2) of timer 123 mode register allows to select whether a value written to timer 2 is written to timer latch and timer synchronously or to the timer latch only. If only the timer latch is written to, the value is set only to the reloadlatch by writing a value to the timer address at that time. The content of timer is reloaded with the next underflow. Usually writing operation to the timer latch and timer synchronously is selected. And a value is written to the timer latch and timer synchronously when a value is written to the timer address. If only the timer latch is written to, it may occur that the value set to the counter is not constant, when the timing with which the reloadlatch is written to and the underflow timing is nearly the same. (2) Timer 2 output control When timer 2 output (TOUT) is enabled, inverted signals are output from TOUT pin each time timer 2 has underflow. For this reason, set the double-function port of TOUT pin to output mode. sPrecautions on timers 1 to 3 When the count source for timer 1 to 3 is switched, it may occur that short pulses are generated in count signals and that the timer count value shows big changes. When timer 1 output is selected as timer 2 or timer 3 count source, short pulses are generated to signals output from timer 1 through writing timer 1. Due to that, the count values for timer 2 and 3 may change very often. Therefore, when the count sources for timer 1 to 3 are set, set the values in order starting from timer 1.
Timer 123 mode register (T123M : address 002916) TOUT output active edge switch bit 0 : start with "H" output 1 : start with "L" output TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled Timer 2 write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 1 count source selection bits 00 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) 01 : f(XIN)/2 (or f(XCIN)/2 in low-speed mode) 10 : f(XCIN) 11 : Not available Not used (returns "0" when read)
Fig. 26. Structure of Timer 123 mode register
f(XIN)/16 (f(XCIN)/16 in low-speed mode) Timer 1 count source selection bits "00" Timer 1 latch (8) "01" f(XIN)/2 Timer 1 (8) (f(XCIN)/2 in low-speed mode) "10" f(XCIN)
Data bus Timer 1 interrupt request Timer 2 interrupt request
Timer 2 count source selection bit Timer 2 latch (8) "0" Timer 2 (8) "1" f(XIN)/16 (f(XCIN)/16 in low-speed mode)
Timer 2 write control bit
TOUT output TOUT output active control bit edge switch bit "0" QS P50/TOUT P50 direction register P50 latch "1" Q "0" T Timer 3 latch (8) Timer 3 (8) "1" Timer 3 count source selection bit Timer 3 interrupt request
TOUT output control bit f(XIN)/16 (f(XCIN)/16 in low-speed mode)
Fig. 27. Block diagram of Timer
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qReal time output port
The 3807 group has two on-chip sets of real time output ports (RTP). The two sets of real time output ports consist of two 16-bit timers A and B and eight 8-bit real time port registers. Synchronous to the reloading of timers A and B, the real time port register values are output from ports P82 to P87, P30 and P31. The real time port registers consist of 8-bit register 0 to 7. Each port with its corresponding bits is shown in figure 26. Timer A and timer B have each two 16-bit timer latches. Figure 28 shows the real time port block diagram and figure 29 and 30 show the structure of the real time port control registers 0 to 3. There are four operating modes for real time ports which are: 8 repeated load mode, 6 repeated load mode, 5 repeated load mode and one-shot pulse generating mode. Each operating mode can be set for timer A and timer B separately. However, switch modes during timer count stop. (1) 8 repeated load mode The output operation for each value of the real time port registers 7 to 0 is performed repeatedly in association with an alternate underflow of the corresponding timer latch 1 or 0. The real time port output pointer changes in sequence as a cycle of 8 repeated load operations as "7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, ...." The initial value at the generation of a start trigger can be specified by setting a value in the output pointer. Figure 31 shows a timing chart of 8 repeated load mode. (2) 6 repeated load mode The output operation for each value of real time port registers 5 to 0 is performed repeatedly in association with an alternate underflow of the corresponding timer latch 1 to 0. The real time port output pointer changes in sequence as a cycle of 6 repeated load operations as "5, 4, 3, 2, 1, 0, 5, 4, 3, 2, 1, 0, 5, 4, ...." The initial value at the generation of a start trigger can be specified by setting a value in the output pointer. Figure 32 shows a timing chart of the 6 repeated load mode. (3) 5 repeated load mode The output operation for each value of real time port registers 4 to 0 is performed repeatedly in association with an alternate underflow of the corresponding timer latch 1 or 0. The real time port output pointer changes in sequence as a cycle of 5 repeated load operations as "4, 3, 2, 1, 0, 4, 3, 2, 1, 0, 4, 3, 2, 1, ...." The initial value at the generation of a start trigger can be specified by setting a value in the output pointer. Figure 33 shows a timing chart of the 5 repeated load mode. (4) One-shot pulse generation mode The output operation for each value of real time port registers 2 to 0 is performed only once in association with trigger generation and an underflow of timer latch 1 or 0. After a trigger is generated, the value of real time port register 1 is output from the real time output port and the output pointer value becomes "0002". At each underflow of the timer, the each value of real time port registers 0 and 2 is output in ascending sequence, then the operation is completed. After completion of the operation, the value of real time port register 2 is continuously output from the real time output port and the output pointer value continues to be "0012" until the next start trigger is generated. In this condition, the real time port function is in the wait status. When this mode is selected, the pointer value is not changed by writing a value into the output pointer. If external trigger is specified as trigger selection when this mode is selected, a rising and falling double edge trigger is generated regardless of the contents of the INT4 interrupt source bit (b7) of the interrupt edge selection register. Figure 34 shows a timing chart of the one-shot pulse generation mode. (5) Selection of timer interrupt mode The timer is a count-down system. The contents of the timer latch are reloaded by the count pulse subsequent to the moment when the contents of the counter becomes "000016". At the same time, the interrupt request bit corresponding to each timer is set to "1." The interrupt request corresponding to the value of the real time port output pointer can also be controlled. For controlling the interrupt request bit, refer to the item pertaining to the timer interrupt mode selection bit of the real time port control register 1,2 shown in figure 29 and 30. (6) Switch of timer count source The timer A and the timer B can select the system clock divided by 2 or 16 as a count source with the timer A, B count source selection bit (b0) of real time port control register 0. [Timer latches] Each of the timer A and the timer B has two 16-bit timer latches. Data is written into the 8 low-order bits and the 8 high-order bits in this order. When the high-order side has been written, the next latch is automatically specified. The writing pointer changes in sequence as "1, 0, 1, 0, 1, ...." The timer latch to be written first can be specified by setting the timer writing pointer. Data is not written directly into the timer A and the timer B. When reading the contents of the timer, the count value at that point of time is read. Read the high-order side first and then the low-order side. The low-order side value is read with the same timing as that for the high-order side value and held at the timer read latch. The data held state is released by reading the loworder side. At a reload operation of the timer A or the timer B. Timer latch 1 is reloaded as the initial value after a trigger is generated. After that, the timer latch is reloaded in sequence as "0, 1, 0, 1, ...." The timer latch value cannot be read out. [Start trigger] The operation of the real time port is started by a start trigger. When a start trigger is generated, the value of the real time port register specified by the output pointer (the value of real time port register 1 in the one-shot pulse generation mode) is output from the real time output port. The value of timer latch 1 is reloaded into the timer A or the timer B and the timer count A, B source stop bit is released, so that the timer count is started. After that, when the timer underflows, data is transferred from the real port register to the real time output port. As a start trigger, either internal trigger or external trigger can be selected by the timer A start trigger selection bit (b2) or timer B start trigger selection bit (b5) of real time port control register 0.
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When the internal trigger is selected, a start trigger is generated by an input signal of the INT4 pin. The start trigger becomes a falling edge when the INT4 interrupt edge selection bit is "0" and a rising edge when this bit is "1". When the external trigger is selected in the one-shot pulse generation mode, the start trigger becomes a rising/falling double edge trigger regardless of the contents of the INT4 interrupt edge selection bit. [Real time port registers] RTP The data to be output to real time ports is written into 8 real time port registers 0 to 7. The correspondence between each bit of real time port registers and each port output is as follows : P31: bit 7 of real time port registers 7 to 0 P30: bit 6 of real time port registers 7 to 0 P87: bit 5 of real time port registers 7 to 0 P86: bit 4 of real time port registers 7 to 0 P85: bit 3 of real time port registers 7 to 0 P84: bit 2 of real time port registers 7 to 0 P83: bit 1 of real time port registers 7 to 0 P82: bit 0 of real time port registers 7 to 0 It can be selected for each bit by real time port control register 3 whether the output of each port is to be used as an ordinary I/O port or a real time port output. [Real time port data pointer] It can be optionally specified by the real time port data pointers A or B and the real time port data pointer A or B switching bit in which real time port register the output data is to be set or form which real time port register the data output is to be started. When writing output data into the real time port register, set the real time port data pointer A, B switch bit to "0" (select the R/W pointer) and also write a value into the 3 bits of the real time port data pointers A, B. With this, the real time port register for writing will be specified. After that, when a value is written into the real time port register (address 002A16), the data is written into the specified real time port register and also the R/W pointer value is automatically decreased by 1. Then writing data is enabled into the next real time port register. A value of "0002" to "1112" can be set int the R/W pointer regardless of the operating mode specified by the timer A, B operating mode selection bit, and the R/W pointer value is automatically decreased by 1 by writing data into the real time port register. However, when a value becomes "0002", the R/W pointer value is decreased by 1 in the numeral range of stages to be used in each operating mode unless the R/W pointer is set again at the subsequent write operation to the real time port register. When "1112 (=7)" is set in the R/W pointer, the R/W pointer operation in each selected mode is as follows : *During 8 repeated load mode 76543210765... *During 6 repeated load mode 76543210543... *During 5 repeated load mode 76543210432.... *During one-shot pulse generation mode 76543210210.... When reading the real time port register, set the real time port data pointer A, B switch bit to "0" (select the R/W pointer) and also writing a value into the 3 bits of the real time port data pointer A, B to specify the real time port register for reading. After that, the value of the specified real time port register can be read by reading the real time port register (address 002A16). In this care, however, the R/W pointer value is not counted down automatically. Accordingly, to read another real time port register, rewrite the R/W pointer beforehand. To specify a read port register to be output to the real time output port, set the real time port data pointer A, B switch bit to "1" (select an output pointer) and also set a value in the 3 bits of the real time port data pointer A or B. When a start trigger is generated, data is output beginning with the real time port register set in the output pointer and the output pointer value is automatically decreased by 1. At each underflow of the timer A or timer B, the output pointer value is automatically decreased by 1. Regarding the case of the one-shot pulse generation mode, however, refer to the item pertaining to the one-shot pulse generation mode. When the real time port data pointer A to B has been read, only the output pointer can be read. sNotes regarding all modes *When the trigger is generated again during timer count operation, the operation is started from the beginning. In this case, put an interval of 3 cycles or more between the generation of a trigger and the generation of the next trigger, If the generation of the next trigger occurs almost concurrently with the underflow timing of the timer, the next real time output may not be performed normally. *To stop the timer count after generation of a start trigger, write "1" in the timer A, B count source stop bit of real time port control register 0 at an interval of 3 cycles or more of the timer count source. *To change the contents of the real time port data pointer A, B switch bit, the real time port data pointer must be specified simultaneously. Therefore, use the LDM/STA instruction instead of the SEB/CLB instruction. *If the timer A, B count source stop bit is changed ("1""0") by a start trigger between the read operation and the write operation of a read-modify-write instruction such as the SEB instruction which is used in real time port control register 0, the timer count will stop, having an effect on the real time output. An maximum interval of 2 cycles of the count source is required before the timer A, B count source stop bit is cleared to "0" which indicates the count operation state after a start trigger is generated regardless of whether the start trigger is an internal trigger or an external trigger. Accordingly, do not use the read-modify-write instruction for real time port control register 0 in this period. If a write operation for real time port control register 0 with any purpose other than stopping the timer count is performed concurrently with the generation of a start trigger, be sure to use such an instruction for writing "0" into the timer A, B count source stop bit as the LDM/STA instruction. Even if "0" is written into the timer A, B count source stop bit, the timer count remains in the stop state without change. *When the timing for writing to the high-order side reload latch is almost equal to the underflow timing, an undesirable value may be set in the timer A or timer B. *If the real time output port is selected by real time port control register 3 after resetting, "L" is output from this pin until a start trigger is generated.
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FUNCTIONAL DESCRIPTION
Data bus XCIN "10"
Main clock division ratio selection bits Timer A, B count source Timer A write pointer (1) Timer A 1H latch (8) Timer A 0H latch (8) Timer A 1L latch (8) Timer A 0L latch (8)
1/2
"0" selection bit
XIN
"00" "01"
1/16
"1" Timer A (16) Timer A interrupt request
P50/RTP0 P31/RTP7 /PWM0
P31 latch PWM0eooO
Real time output Real time port output selection bit (P31)
Timer A count source stop bit
Timer A read-out latch (8)
Timer B write pointer (1) Timer B 1H latch (8) Timer B 1L latch (8) Timer B 0L latch (8)
P31 direction register P30/RTP6 P30 latch PWM1eooO
Real time output Real time port output selection bit (P30)
Timer B 0H latch (8)
Timer B (16) Timer B count source stop bit Timer B read-out latch (8)
Timer B interrupt request
P30 direction register P87/RTP5 P87 latch 7
Real time output Real time port output selection bit (P87)
Real time port * port allocation selection bit
"1" "0" 0
Real time port R/W pointer A (3) Real time port R/W pointer B (3)
P87 direction register P86/RTP4 P86 latch
Real time output Real time port output selection bit (P86)
Real time port register 0 (8) Real time port register 1 (8) Real time port register 2 (8) Real time port register 3 (8) Real time port register 4 (8) Real time port register 5 (8) Real time port register 6 (8) Real time port register 7 (8)
Real time port * port allocation selection bit
P86 direction register P85/RTP3 P85 latch
"1" "0"
Real time port output pointer A (3) Real time port output pointer B (3)
Real time output Real time port output selection bit (P85)
Output latch (8)
P85 direction register P84/RTP2 P84 latch
Real time output Real time port output selection bit (P84)
P84 direction register P83/RTP1 P83 latch
When a start trigger bit is set to "1" (internal trigger is selected) When an external start trigger is generated (external trigger is selected)
A timer latch value is loaded into the timer A timer latch value is loaded into the timer
Real time output Real time port output selection bit (P83)
operation P83 direction register P82/RTP0 P82 latch
0
1
stop
at reset Timer count source stop bit is set to "1".
Real time output Real time port output selection bit (P82)
State transition of timer count source stop bit
P82 direction register
Fig. 28. Block diagram of Real time output port
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b7 b0 Real time port control register 0 (RTPCON0 : address 002B16) Timer A, B count source selection bit 0: f(XIN)/2 or f(XCIN)/2 1: f(XIN)/16 or f(XCIN)/16 Real time port * port allocation selection bit 0: 4-4 port division (P82 to P85 correspond to timer A; P86, P87, P30, P31 correspond to timer B) 1: 2-6 port division (P82 to P87 correspond to timer A; P30, P31 correspond to timer B) Timer A start trigger selection bit 0: Internal trigger (trigger is generated by setting bit 3 to "1") 1: External trigger (trigger start by external input INT4) (note) Timer A start trigger bit ("0" at read-out) 0: Not triggered 1: Timer A start (when bit 2="0") Timer A count source stop bit 0: Count operation (when a start trigger is generated, "0" is set automatically) 1: Count stop Timer B start trigger selection bit 0: Internal trigger (trigger is generated by setting bit 6 to "1") 1: External trigger (trigger start by external input INT4) (note) Timer B start trigger bit ("0" at read-out) 0: Not triggered 1: Timer B start (when bit 5="0") Timer B count source stop bit 0: Count operation (when a start trigger is generated, "0" is set automatically) 1: Count stop Note: Rising or falling edge of external input can be switched by the INT4 interrupt edge selection bit of interrupt edge selection register (however, at one-shot pulse generating mode the timer is triggered at both rising and falling edge). b7 b0 Real time port control register 1 (RTPCON1 : address 002C16) Timer A operation mode selection bit 00: 8 repeated load mode 01: 6 repeated load mode 10: 5 repeated load mode 11: One-shot pulse generating mode Real time port data pointer A switch bit ("1" at read-out ) 0: R/W pointer 1: Output pointer Timer A interrupt mode selection bit 0: Interrupt request occurs with RTP output pointer value "0002" 1: Interrupt request occurs regardless of RTP output pointer value Real time port data pointer A (output pointer value at read-out) 000: indicates real time port register 0 001: indicates real time port register 1 010: indicates real time port register 2 011: indicates real time port register 3 100: indicates real time port register 4 101: indicates real time port register 5 110: indicates real time port register 6 111: indicates real time port register 7 Timer A write pointer 0: indicates timer A0 latch 1: indicates timer A1 latch
Fig. 29. Structure of Real time output port related register (1)
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b7 b0 Real time port control register 2 (RTPCON2 : address 002D16) Timer B operating mode selection bit 00: 8 repeated load mode 01: 6 repeated load mode 10: 5 repeated load mode 11: One-shot pulse generating mode Real time port data pointer B switch bit ("1" at read-out ) 0: R/W pointer 1: Output pointer Timer B interrupt mode selection bit 0: Interrupt request occurs with RTP output pointer value "0002" 1: Interrupt request occurs regardless of RTP output pointer value Real time port data pointer B (output pointer value at read-out) 000: indicates real time port register 0 001: indicates real time port register 1 010: indicates real time port register 2 011: indicates real time port register 3 100: indicates real time port register 4 101: indicates real time port register 5 110: indicates real time port register 6 111: indicates real time port register 7 Timer B write pointer 0: indicates timer B0 latch 1: indicates timer B1 latch b7 b0 Real time port control register 3 (RTPCON3 : address 002E16) Real time port output selection bit (P82) 0: I/O port 1: Real time output port Real time port output selection bit (P83) 0: I/O port 1: Real time output port Real time port output selection bit (P84) 0: I/O port 1: Real time output port Real time port output selection bit (P85) 0: I/O port 1: Real time output port Real time port output selection bit (P86) 0: I/O port 1: Real time output port Real time port output selection bit (P87) 0: I/O port 1: Real time output port Real time port output selection bit (P30) 0: I/O port 1: Real time output port Real time port output selection bit (P31) 0: I/O port 1: Real time output port
Fig. 30. Structure of Real time output port related register (2)
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Timer A operating mode selection bit: in case of 8 repeated load mode 4-4 port division
Synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts. Timer count source stop bit
Timer A count value
A1 #7 1 A0 #6 1 A1 #5 0 A0 #4 0 A1 #3 0 A0 #2 0 A1 #1 0 A0 #0 1 A1 #7 1 A0 #6 1 A1 #5 0
Port P82 / RTP0 Port P83 / RTP1 Port P84 / RTP2 Port P85 / RTP3
0
1
1
1
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
Real time port output pointer A
7
6
5
4
3
2
1
0
7
6
5
4
#7--0: Data of real time port registers 7 to 0
Fig. 31. 8 repeated load mode operation
Timer A operating mode selection bit: in case of 6 repeated load mode 4-4 port division (3 ports out of P82/RTP0 to P85/RTP3 are used)
Synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts. Timer count source stop bit
Timer A count value
A1 #5 1 A0 #4 1 A1 #3 0 A0 #2 0 A1 #1 0 A0 #0 1 A1 #5 1 A0 #4 1 A1 #3 0 A0 #2 0 A1 #1 0
Port P82 / RTP0 Port P83 / RTP1 Port P84 / RTP2
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
Real time port output pointer A
5
4
3
2
1
0
5
4
3
2
1
0
#5--0: Data of real time port registers 5 to 0
Fig. 32. 6 repeated load mode operation
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Timer A operating mode selection bit: in case of 5 repeated load mode 2-6 division (5 ports out of P82/RTP0 to P87/RTP5 are used)
Synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts. Timer count source stop bit
Timer A count value
A1 #4 1 A0 #3 0 A1 #2 0 A0 #1 0 A1 #0 1 A0 #4 1 A1 #3 0 A0 #2 0 A1 #1 0 A0 #0 1
Port P82 / RTP0 Port P83 / RTP1 Port P84 / RTP2 Port P85 / RTP3 Port P86 / RTP4 Real time port output pointer A
1
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
1
4
3
2
1
0
4
3
2
1
0
4
#4--0: Data of real time port registers 4 to 0
Fig. 33. 5 repeated load mode operation
Timer A operating mode selection bit: in case of one-shot pulse generating mode
Synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts.
External start trigger input INT4
Timer count source stop bit
Counting stops when timer A0 latch has underflow Counting stops when timer A0 latch has underflow
Timer A count value
A1 #1 A0 #0 1 #2 0 A1 #1 0 A0 #0 1 #2 0
Port P82 / RTP0
0
Port P83 / RTP1 Real time port output pointer A
1
1
0
1
1
0
0
2
1
0
2
1
#2--0: Data of real time port registers 2 to 0
Fig. 34. One-shot pulse generating mode operation
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Serial I/O qSerial I/O1
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation during Serial I/O1 operation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to "1." For clock synchronous serial I/O, the transmitter and the receiver must use the same clock for serial I/O1 operation. If an internal clock is used, transmit/receive is started by a write signal to the Transmit/Receive buffer register (TB/RB) (address:001816).
Data bus Address 001816 Receive buffer register P44/RXD Receive shift register Shift clock P46/SCLK1 Serial I/O1 synchronous clock selection bit Division ratio 1/(n+1) BRG count source selection bit f(XIN) XIN Baud rate generator 1/4 (f(XCIN) in low-speed mode) Address 001C16 1/4 P47/SRDY1 F/F Falling edge detector Shift clock P45/TXD Transmit shift register Transmit buffer register Address 001816 Data bus Clock control circuit Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Clock control circuit Serial I/O 1 control register Address 001A16
Receive buffer full flag (RBF) Receive interrupt request (RI)
Fig. 35. Block diagram of clock synchronous serial I/O1
Transmit/Receive shift clock (1/2--1/2048 of internal clock or external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Receive enable signal SRDY1 Write-in signal to transmit/receive buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection
TBE = 1 TSC = 0
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" .
Fig. 36. Operation of clock synchronous serial I/O1 function
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(2) Asynchronous Serial I/O (UART) Mode Asynchronous serial I/O1 mode (UART) can be selected by clearing the Serial I/O1 mode selection bit (b6) of the Serial I/O1 control register to "0." Eight serial data transfer formats can be selected and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer (the two buffers have the same address in memory). Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a character while the next character is being received.
Data bus Address 001816 Receive buffer register OE Character length selection bit 7 bit STdetector Receive shift register 8 bit PE FE SP detector Clock control circuit Serial I/O1 synchronous clock selection bit Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 UART control register Address 001B16
P44/RXD
P46/SCLK1
f(XIN)
BRG count source selection bit 1/4
(f(XCIN) in low-speed mode)
Division ratio 1/(n+1) Baud rate generator Address 001C16 ST/SP/PA generator 1/16 Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916
P45/TXD Character length selection bit
Transmit shift register Transmit buffer register Address 001816 Data bus
Fig. 37. Block diagram of UART serial I/O1
Transmit or receive clock Write-in signal to transmit buffer register TBE=0 TSC=0 TBE=1 Serial output TXD ST D0 D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit SP ST D0 D1 SP * Generated at 2nd bit in 2-stop bit mode TBE=0 TBE=1 TSC=1*
Read-out signal from receive buffer register
RBF=0 RBF=1 Serial input RXD ST D0 D1 SP ST D0 D1 SP RBF=1
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer register when TSC=1, 0.5 to 1,5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 38. Operation of UART serial I/O1 function
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[Transmit Buffer Register/Receive Buffer Register] TB/RB (001816) The transmit buffer and the receive buffer are located in the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Serial I/O 1 Status Register] SIO1STS (001916) The read-only serial I/O1 status register consists of seven flags (b0 to b6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (b4 to b6) are only valid in UART mode. The receive buffer full flag (b1) is cleared to "0" when the receive buffer is read. The error detection is performed at the same time data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A writing to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (b3 to b6, respectively). Writing "0" to the serial I/O1 enable bit (SIOE : b7 of the serial I/O1 control register) also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit (b4) of the serial I/O1 control register has been set to "1", the transmit shift register shift completion flag (b2) and the transmit buffer empty flag (b0) become "1." [Serial I/O1 Control Register] SIO1CON (001A16) The serial I/O1 control register contains eight control bits for serial I/O1 functions. [UART Control Register] UARTCON (001B16) The UART control register consists of four control bits (b0 to b3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (b4) is always valid and sets the output structure of the P45/TxD pin. [Baud Rate Generator] BRG (001C16) The baud rate generator determines the baud rate for serial transfer. With the 8-bit counter having a reload register the baud rate generator divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator.
b7
b0
Serial I/O1 status register (SIO1STS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read)
b7
b0
Serial I/O1 control register (SIO1CON : address 001A16) BRG count source selection bit (CSS) (f(XCIN) in low-peed mode) 0: f(XIN) 1: f(XIN)/4 ((XCIN)/4 in low-speed mode) Serial I/O1 synchronous clock selection bit (SCS) 0: BRG/ 4 (when clock synchronous serial I/O is selected) BRG/16 (UART is selected) 1: External clock input (when clock synchronous serial I/O is selected) External clock input/16 (UART is selected) SRDY1 output enable bit (SRDY) 0: P47 pin operates as ordinaly I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44 to P47 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P44 to P47 operate as serial I/O pins)
b7
b0
UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity cheching disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return "1" when read)
Fig. 39. Structure of serial I/O1 related register
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qSerial I/O2
The serial I/O2 can be operated only as the clock synchronous type. As a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection bit (b6) of serial I/O2 control register 1. The internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selection bit (b2, b1, b0) of serial I/O2 control register 1. Regarding SOUT2 and SCLK2 being output pins, either CMOS output format or N-channel open-drain output format can be selected by the P71/SOUT2, P72/SCLK2 P-channel output disable bit (b7) of serial I/O2 control register 1. When the internal clock has been selected, a transfer starts by a write signal to the serial I/O2 register (address 001F16). After completion of data transfer, the level of the SOUT2 pin goes to high impedance automatically but bit 7 of the serial I/O2 control register 2 is not set to "1" automatically. When the external clock has been selected, the contents of the serial I/O2 register is continuously sifted while transfer clocks are input. Accordingly, control the clock externally. Note that the SOUT2 pin does not go to high impedance after completion of data transfer. To cause the SOUT2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial I/O2 control register 2 to "1" when SCLK2 is "H" after completion of data transfer. After the next data transfer is started (the transfer clock falls), bit 7 of the serial I/O2 control register 2 is set to "0" and the SOUT2 pin is put into the active state. Regardless of the internal clock to external clock, the interrupt request bit is set after the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred. In case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial I/O2 register becomes a fractional number of bits close to MSB if the transfer direction selection bit of serial I/O2 control register 1 is LSB first, or a fractional number of bits close to LSB if the said bit is MSB first. For the remaining bits, the previously received data is shifted. At transmit operation using the clock synchronous serial I/O, the SCMP2 signal can be output by comparing the state of the transmit pin SOUT2 with the state of the receive pin SIN2 in synchronization with a rise of the transfer clock. If the output level of the SOUT2 pin is equal to the input level to the SIN2 pin, "L" is output from the SCMP2 pin. If not, "H" is output. At this time, an INT2 interrupt request can also be generated. Select a valid edge by bit 2 of the interrupt edge selection register (address 003A16). [Serial I/O2 Control Registers 1, 2] SIO2CON1 / SIO2CON2 The serial I/O2 control registers 1 and 2 are containing various selection bits for serial I/O2 control as shown in Figure 40.
b7 b0
Serial I/O2 control register 1 (SIO2CON1 : address 001D16) Internal synchronous clock selection bit
b2 b1 b0
0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 1 0: f(XIN)/128 f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK2 output pin SRDY2 output enable bit 0: P73 pin is normal I/O pin 1: P73 pin is SRDY2 output pin Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P71/SOUT2 ,P72/SCLK2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode )
b7
b0
Serial I/O2 control register 2 (SIO2CON2 : address 001E16) Optional transfer bits
b2 b1 b0
0 0 0: 1 bit 0 0 1: 2 bit 0 1 0: 3 bit 0 1 1: 4 bit 1 0 0: 5 bit 1 0 1: 6 bit 1 1 0: 7 bit 1 1 1: 8 bit Not used ( returns "0" when read) Serial I/O2 I/O comparison signal control bit 0: P51 I/O 1: SCMP2 output SOUT2 pin control bit (P71) 0: Output active 1: Output high-impedance
Fig. 40. Structure of Serial I/O2 control registers 1, 2
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3807 GROUP USER'S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Internal synchronous clock selection bit
1/8
XCIN
Divider
1/16 "10" "00" "01" 1/32 1/64 1/128 1/256
Main clock division ratio selection bits (Note)
Data bus
XIN
P73 latch
"0"
Serial I/O2 synchronous clock selection bit
P73/SRDY2
"1" "0"
SCLK2
SRDY2 Synchronous circuit "1" SRDY2 output enable bit External clock
P72 latch
"0"
Optional transfer bits (3) Serial I/O counter 2 (3) Serial I/O2 interrupt request
P72/SCLK2
"1" Serial I/O2 port selection bit
P71 latch
"0"
P71/SOUT2
"1" Serial I/O2 port selection bit
P70/SIN2
Serial I/O2 register (8)
P51 latch
"0"
P51/SCMP2/INT2
"1" Serial I/O2 I/O comparison signal control bit
D Q
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
Fig. 41. Block diagram of Serial I/O2
Transfer clock (Note 1) Write-in signal to serial I/O2 register
(Note 2)
Serial I/O2 output SOUT2 Serial I/O2 input SIN2
D0
D1
.
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected by setting bits 0 to 2 of serial I/O2 control register 1. 2: When the internal clock is selected as a transfer clock, the SCOUT2 pin has high impedance after transfer completion.
Fig. 42. Timing chart of Serial I/O2
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HARDWARE
FUNCTIONAL DESCRIPTION
SCMP2 SCLK2 SOUT2 SIN2
Judgement of I/O data comparison
Fig. 43. SCMP2 output operation
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3807 GROUP USER'S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
A-D Converter
[A-D Conversion Register] AD (address 003516) The A-D conversion register is a read-only register that contains the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. [A-D Control Register] ADCON The A-D control register controls the A-D conversion process. Bits 0 to 3 of this register select specific analog input pins. Bit 4 signals the completion of an A-D conversion. The value of this bit remains at "0" during an A-D conversion, then changes to "1" when the A-D conversion is completed. Writing "0" to this bit starts the A-D conversion. When bit 6, which is the AD external trigger valid bit, is set to "1", this bit enables A-D conversion at a falling edge of an ADT input. Set ports which is also used as ADT pins to input when using an A-D external trigger. Bit 5 is the ADVREF input switch bit. Writing "1" to this bit, this bit always causes ADVREF connection. Writing "0" to this bit causes ADVREF connection only during A-D conversion and cut off when A-D conversion is completed. [Comparison Voltage Generator] The comparison voltage generator divides the voltage between AVSS and ADVREF by 256, and outputs the divided voltages. [Channel Selector] The channel selector selects one of the input ports AN12 to AN0 and inputs it to the comparator. [Comparator and Control Circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD conversion interrupt request bit to "1." Note that the comparator is constructed linked to a capacitor, so set f(XIN) to at least 500kHz during A-D conversion. Use a CPU system clock dividing the main clock XIN as the internal clock . sNote When the A-D external trigger is invalidated by the AD external trigger valid bit, any interrupt request is not generated at a fall of the ADT input. When the AD external trigger valid bit is set to "1" beforehand, A-D conversion is not started by writing "0" into the AD conversion completion bit and "0" is not written into the AD conversion completion bit. Do not set "0" in the AD conversion completion bit concurrently with the timing at which the AD external trigger valid bit is rewritten. Put an interval of at least 50 cycles to more of the internal clock between a start of A-D conversion and the next start of A-D conversion.
b7
b0
A-D control register (ADCON : address 003416) Analog input pin selection bit 0000: P73/SRDY2/ADT/AN0 0001: P74/AN1 0010: P75/AN2 0011: P76/AN3 0100: P77/AN4 0101: P60/AN5 0110: P61/AN6 0111: P62/AN7 1000: P63/CMPIN/AN8 1001: P64/CMPREF/AN9 1010: P65/DAVREF/AN10 1011: P80/DA3/AN11 1100: P81/DA4/AN12 AD conversion completion bit 0: Conversion in progress 1: Conversion completed ADVREF input switch bit 0: OFF 1: ON AD external trigger valid bit 0: A-D external trigger invalid 1: A-D external trigger valid Interrupt source selection bit 0: Interrupt request at A-D conversion completed 1: Interrupt request at ADT input falling
Fig. 44. Structure of A-D control register
Data bus
b7 A-D control register
b0
4 P73/SRDY2/ADT/AN0 P74/AN1 P75/AN2 P76/AN3 P77/AN4 P60/AN5 P61/AN6 P62/AN7 P63/CMPIN/AN8 P64/CMPREF/AN9 P65/DAVREF/AN10 P80/DA3/AN11 P81/DA4/AN12 A-D control circuit ADT/A-D interrupt request
Channel selector
Comparator
A-D conversion register 8 Resistor ladder
AVSS ADVREF
Fig. 45. Block diagram of A-D converter
3807 GROUP USER'S MANUAL
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HARDWARE
FUNCTIONAL DESCRIPTION
D-A Converter
The 3807 group has an on-chip D-A converter with 8-bit resolution and 4 channels (DAi (i=1--4)). The D-A converter is performed by setting the value in the D-A conversion register. The result of D-A converter is output from DAi pin by setting the DAi output enable bits to "1." When using the D-A converter, the corresponding port direction register bit (P65/DAVREF/AN10, P56/DA1, P57/DA2, P80/DA3/AN11, P81/DA4/AN12) should be set to "0" (input status). The output analog voltage V is determined by the value n (base 10) in the D-A conversion register as follows: V=DAVREF x n/256 (n=0 to 255) Where DAVREF is the reference voltage. At reset, the D-A conversion registers are cleared to "0016", the DAi output enable bits are cleared to "0", and DAi pin is set to input (high impedance). The DA output is not buffered, so connect an external buffer when driving a low-impedance load.
b7
b0 D-A control register (DACON : address 003316) DA1 output enable bit DA2 output enable bit DA3 output enable bit DA4 output enable bit Not used (return "0" when read) 0 : Output disabled 1 : Output enabled
Fig. 46. Structure of D-A control register
Data bus
D-A1 conversion register (003616) D-A2 conversion register (003716) D-A3 conversion register (003816) D-A4 conversion register (003916)
D-A i conversion register (8) DA i output enable bit P56/DA1 P57/DA2 P80/DA3/AN11 P81/DA4/AN12
R-2R resistor ladder
Fig. 47. Block diagram of D-A converter
DA i output enable bit (Note)
P56/DA1 P57/DA2 P80/DA3/AN11 P81/DA4/AN12
"0"
R 2R MSB
R 2R
R 2R
R 2R
R 2R
R
R
2R
"1"
2R
2R
2R LSB
D-A i conversion register (Note) AVSS P65/DAVREF/AN10 Note: i=1 to 4
"0"
"1"
Fig. 48. Equivalent connection circuit of D-A converter
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3807 GROUP USER'S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Analog Comparator
An analog comparator circuit which is independent of peripheral circuits in the microcomputer is incorporated (Note). An analog comparator outputs the result of comparison with an input voltage of CMPREF pin which is specified as a reference voltage and an input voltage of CMPIN pin to CMPOUT pin. The result is "1" when the input voltage to port CMPIN is higher than the voltage applied to port CMPREF and "0" when the voltage is lower. Because the analog comparator consists of an analog MOS circuit, set the input voltage to the CMPIN pin and the CMPREF pin within the following range : VSS +1.2 V to CMPVCC-0.5V sNote The analog comparator circuit is separated from the MCU internal peripheral circuit in the microcomputer. Accordingly, even if the microcomputer runs away, the analog comparator is still in operation. For this reason, the analog comparator can be used for safety circuit design.
CMPVCC P63/CMPIN /AN8 + - P64/CMPREF /AN9 CMPOUT AVSS
Fig. 49. Block diagram of Analog comparator
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HARDWARE
FUNCTIONAL DESCRIPTION
Watchdog Timer
The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and a 8-bit watchdog timer H. qStandard operation of watchdog timer When any data is not written into the watchdog timer control register (address 001716) after resetting, the watchdog timer is in the stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 001716) and an internal resetting takes place at an underflow of the watchdog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 001716) may be started before an underflow. When the watchdog timer control register (address 001716) is read, the values of the 6 high-order bits of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read. (1) Initial value of watchdog timer At reset or writing to the watchdog timer control register (address 001716), each watchdog timer H and L is set to "FF16." (2) Watchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register (address 001716) permits selecting a watchdog timer H count source. When this bit is set to "0", the count source becomes the underflow signal of watchdog timer L. The detection time is set then to f(XIN)=131.072 ms at 8 MHz frequency and f(XCIN)=32.768 s at 32 kHz frequency. When this bit is set to "1", the count source becomes the signal divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case is set to f(XIN)=512 s at 8 MHz frequency and f(XCIN)=128 ms at 32 KHz frequency. This bit is cleared to "0" after resetting. (3) Operation of STP instruction disable bit Bit 6 of the watchdog timer control register (address 001716) permits disabling the STP instruction when the watchdog timer is in operation. When this bit is "0", the STP instruction is enabled. When this bit is "1", the STP instruction is disabled. Once the STP instruction is executed, an internal resetting takes place. When this bit is set to "1", it cannot be rewritten to "0" by program. This bit is cleared to "0" after resetting.
XCIN "10" Main clock division ratio selection bits (Note) XIN
"FF16" is set when watchdog timer control register is written to. "0" Watchdog timer L (8) 1/16 "00" "01" "1" Watchdog timer H (8)
Data bus "FF16" is set when watchdog timer control register is written to.
Watchdog timer H count source selection bit
STP instruction disable bit STP instruction Reset circuit Internal reset
RESET
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of CPU mode register.
Fig. 50. Block diagram of Watchdog timer
b7
b0
Watchdog timer control register (WDTCON : address 001716)
Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16
Fig. 51. Structure of Watchdog timer control register
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3807 GROUP USER'S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Clock output function
The internal clock can be output from I/O port P34. Control of I/O ports and clock output function can be performed by port P2P3 control register (address 001516).
b7 b0 Port P2P3 control register (P2P3C : address 001516) P34 clock output control bit 0: I/O port 1: Clock output Output clock frequency selection bits 000: 001: f(XCIN) 010: "L" fixed for output 011: "L" fixed for output 100: f(XIN) (f(XCIN) in low-speed mode) 101: f(XIN)/2 (f(XCIN)/2 in low-speed mode) 110: f(XIN)/4 (f(XCIN)/4 in low-speed mode) 111: f(XIN)/16 (f(XCIN)/16 in low-speed mode) Not used (return "0" when read) P2*P32 input level selection bit 0: CMOS level input 1: TTL level input
(1) I/O ports or clock output function selection The P34 clock output control bit (b0) of port P2P3 control register selects the I/O port or clock output function. When clock output function is selected, the clock is output regardless of the port P34 direction register settings. Directly after bit 0 is written to, the port or clock output is switched synchronous to a falling edge of clock frequency selected by the output clock frequency selection bit. When memory expansion mode or microprocessor mode is selected in CPU mode register (b1, b0), clock output is selected on regardless of P34 clock output control bit settings or port P34 direction register settings. (2) Selection of output clock frequency The output clock frequency selection bits (b3, b2, b1) of port P2P3 control register select the output clock frequency. The output waveform when f(XIN) or f(XCIN) is selected, depends on XIN or XCIN input waveform however; all other output waveform settings have a duty cycle of 50%.
Fig. 52. Structure of Port P2P3 control register
P34 direction register P34 clock output control bit Microprocessor mode/memory expansion mode
P34 port latch Output clock frequency selection bits "000" XCIN Main clock division ratio selection bits (Note)
Low-speed mode
"001"
P34/CKOUT/o
"100"
High-speed or middle-speed mode
1/2 1/4 1/16
"101" "110" "111" "010" "011"
XIN
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of CPU mode register.
Fig. 53. Block diagram of Clock output function
3807 GROUP USER'S MANUAL
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HARDWARE
FUNCTIONAL DESCRIPTION
Reset Circuit
______
To reset the microcomputer, RESET pin should be held at an "L" ______ level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage should be between 2.7 V and 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.54 V for VCC of 2.7 V.
Poweron Power source voltage 0V Reset input voltage 0V (Note)
RESET
VCC
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
VCC Power source voltage detection circuit
Fig. 54. Reset circuit example
XIN
RESET Internal reset
Address
?
?
?
?
FFFC
FFFD
ADH,L
Reset address from the vector table.
Data
?
?
?
?
ADL
ADH
SYNC
XIN: 10.5 to 18.5 clock cycles Notes 1: The frequency relation of f(XIN) and f() is f(XIN)=8 * f(). 2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 55. Reset sequence
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HARDWARE
FUNCTIONAL DESCRIPTION
Address Register contents (1) Port P0 (2) Port P0 direction register (3) Port P1 (4) Port P1 direction register (5) Port P2 (6) Port P2 direction register (7) Port P3 (8) Port P3 direction register (9) Port P4 (10) Port P4 direction register (11) Port P5 (12) Port P5 direction register (13) Port P6 (14) Port P6 direction register (15) Port P7 (16) Port P7 direction register (17) Port P8 (18) Port P8 direction register (19) Timer XY control register (20) Port P2P3 control register (21) Pull-up control register (22) Watchdog timer control register (23) Serial I/O1 status register (24) Serial I/O1 control register (25) UART control register (26) Serial I/O2 control register 1 (27) Serial I/O2 control register 2 (28) Timer X (low-order) (29) Timer X (high-order) (30) Timer Y (low-order) (31) Timer Y (high-order) (32) Timer 1 (33) Timer 2 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 (34) Timer 3 (35) Timer X mode register (36) Timer Y mode register (37) Timer 123 mode register (38) Real time port register 0--7 (39) Real time port control register 0 (40) Real time port control register 1 R/W pointer Output pointer (41) Real time port control register 2 R/W pointer Output pointer (42) Real time port control register 3 (43) Timer A (low-order) (44) Timer A (high-order) (45) Timer B (low-order) (46) Timer B (high-order) (47) D-A control register (48) A-D control register (49) D-A1 conversion register (50) D-A2 conversion register (51) D-A3 conversion register (52) D-A4 conversion register (53) Interrupt edge selection register (54) CPU mode register (55) Interrupt request register 1 (56) Interrupt request register 2 (57) Interrupt control register 1 (58) Interrupt control register 2 (59) Processor status register (60) Program counter 002E16 002F16 003016 003116 003216 003316 002D16 1 111 111 0016 FF16 FF16 FF16 FF16 0016 Address Register contents 002616 002716 002816 002916 002A16 FF16 0016 0016 0016 0016
002B16 1 0 0 1 0 0 0 0 002C16 1 111 111 0000 0000
001416 0 0 0 0 0 0 1 1 001516 * 0 0 0 0 0 0 0 001616 0016
003416 0 0 0 1 0 0 0 0 003616 003716 003816 003916 003A16 0016 0016 0016 0016 0016
001716 0 0 1 1 1 1 1 1 001916 1 0 0 0 0 0 0 0 001A16 0016
001B16 1 1 1 0 0 0 0 0 001D16 0016
003B16 0 1 0 0 1 0 * 0 003C16 003D16 003E16 003F16 (PS) 5
5 5
0016 0016 0016 0016
5 5
001E16 0 0 0 0 0 1 1 1 002016 002116 002216 002316 002416 002516 FF16 FF16 FF16 FF16 FF16 0116
15
5
(PCH) (PCL)
FFFD16 contents FFFC16 contents
* The initial values depend on level of port CNVSS. X: Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 56. Internal status at reset
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HARDWARE
FUNCTIONAL DESCRIPTION
Clock Generating Circuit
The 3807 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after poweron, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. qFrequency control (1) Middle-speed mode The internal clock is the frequency of XIN divided by 8. After reset, this mode is selected. (2) High-speed mode The internal clock is half the frequency of XIN. (3) Low-speed mode The internal clock is half the frequency of XCIN. sNote If you switch the mode between middle/high-speed and low-speed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after poweron and at returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3f(XCIN). (4) Low power consumption mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to "1." When the main clock XIN is restarted (by setting the main clock stop bit to "0"), set enough time for oscillation to stabilize. By clearing furthermore the XCOUT drivability selection bit (b3) of CPU mode register to "0", low power consumption operation of less than 55 A (VCC=3 V, XCIN=32 kHz) can be realized by reducing the drivability between XCIN and XCOUT. At reset or during STP instruction execution this bit is set to "1" and a reduced drivability that has an easy oscillation start is set. The sub-clock XCIN-XCOUT oscillating circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate. qOscillation control (1) Stop mode If the STP instruction is executed, the internal clock stops at an "H" level, and XIN and XCIN oscillators stop. Timer 1 is set to "FF16" and timer 2 is set to "0116." Either XIN or XCIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except timer 3 count source selection bit (b4) are cleared to "0". Set the timer 2/INT3 interrupt source bit to "1" and timer 1/INT2 as well as timer 2/INT3 interrupt enable bit to disabled ("0") before executing the STP instruction. Oscillator restarts when an external interrupt is received, but the internal clock is not supplied to the CPU (remains at "H") until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. The internal clock is supplied for the first time, when timer 2 underflows. Therefore make sure not to set the timer 2/INT3 interrupt request bit to "1" before the STP instruction stops the oscillator. When the ______ oscillator is restarted by reset apply "L" level to port RESET until the oscillation is stable since a wait time will not be generated. (2) Wait mode If the WIT instruction is executed, the internal clock stops at an "H" level. The states of XIN and XCIN are the same as the state before executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted.
XCIN Rf
XCOUT Rd CCOUT
XIN
XOUT
CCIN
CIN
COUT
Fig. 57. Ceramic resonator circuit
XCIN Rf
XCOUT Rd
XIN
XOUT open
CCIN
External oscillation circuit CCOUT VCC VSS
Fig. 58. External clock input circuit
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3807 GROUP USER'S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
XCIN XCOUT
"0"
"1"
Port XC switch bit
Timer 1 count source selection bits
Timer 2 count source selection bit
"0"
XIN
XOUT
Main clock division ratio selection bits (note) Low-speed mode
"10" "01"
Timer 1
1/2
High-speed or middle-speed mode
1/4
1/2
"00" "1"
Timer 2
Main clock division ratio selection bits (note) Middle-speed mode High-speed or low-speed mode Main clock stop bit
Timing (internal clock)
Q
S R
STP instruction WIT instruction
SQ R
QS R
STP instruction
Reset Interrupt disable flag l Interrupt request
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of CPU mode register. When low-speed mode is selected, set port Xc switch bit (b4) to "1".
Fig. 59. System clock generating circuit block diagram (Single-chip mode)
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HARDWARE
FUNCTIONAL DESCRIPTION
Reset
Middle-speed mode (f()=1MHz) CM7=0 CM6=1 CM5=0(8MHz oscillating) CM4=0(32kHz stopped)
CM6 "1"
"0"
High-speed mode (f()=4MHz) CM7=0 CM6=0 CM5=0(8MHz oscillating) CM4=0(32kHz stopped)
CM " "1 M 6 C" "1
4
"0
"
CM4 "1"
"0
"
"0
"
High-speed mode (f()=4MHz) CM7=0 CM6=0 CM5=0(8MHz oscillating) CM4=1(32kHz oscillating)
Middle-speed mode (f()=1MHz) CM7=0 CM6=1 CM5=0(8MHz oscillating) CM4=1(32kHz oscillating)
CM6 "1"
"0"
Low-speed mode (f()=16kHz) CM7=1 CM6=0 CM5=0(8MHz oscillating) CM4=1(32kHz oscillating)
CM7 "1"
CM "0 7 " CM "1 6 "1 " " "0 "
"0"
CM4 "1"
"
C "0 M 4 " C "1 M 6 "1 "
"0"
"0"
b7
b4 CPU mode register (CPUM : address 003B16)
CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN- XOUT) stop bit 0 : Operating 1 : Stopped CM7 CM6: Main clock division ratio selection bit b7 b6 0 0 : = f(XIN)/2 (High-speed mode) 0 1 : = f(XIN)/8 (Middle-speed mode) 1 0 : = f(XCIN)/2 (Low-speed mode) 1 1 : Not available
Low-speed mode (f()=16kHz) CM7=1 CM6=0 CM5=1(8MHz stopped) CM4=1(32kHz oscillating)
Note 1:Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2:The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3:Timer operates in the wait mode. 4:When the stop mode is ended, a delay of approximately 1 ms occurs by Timer 1 and Timer 2 in middle/high-speen mode. 5:When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode. 6:Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/highspeed mode. 7:The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. indicates the internal clock.
Fig. 60. State transitions of system clock
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3807 GROUP USER'S MANUAL
CM5 "1"
"0"
HARDWARE
FUNCTIONAL DESCRIPTION
Processor Mode
Single-chip mode, memory expansion mode, and microprocessor mode can be selected by changing the contents of the processor mode bits (CM0 and CM1 : b1 and b0 of address 003B16). In memory expansion mode and microprocessor mode, memory can be expanded externally through ports P0 to P3. In these modes, ports P0 to P3 lose their I/O port functions and become bus pins. Table. 9. Port functions in memory expansion mode and microprocessor mode Port Name Function Port P0 Outputs 8-bits low-order byte of address. Port P1 Port P2 Port P3 Outputs 8-bits high-order byte of address. Operates as I/O pins for data D7 to D0 (including instruction code) P30 and P31 function only as output pins (except that the port latch cannot be read). ____ P32 is the ONW input pin. P33 is the RESTOUT output pin. (Note) P34 is the output pin. P35 is the ___ output pin. SYNC ___ P36 is the WR output pin, and P37 is the RD output pin. Note : If CNVSS is connected to VSS, the microcomputer goes to single-chip mode after a reset, so this pin cannot be used as the RESETOUT output pin. (1) Single-chip mode Select this mode by resetting the microcomputer with CNVSS connected to VSS. (2) Memory expansion mode Select this mode by setting the processor mode bits (b1, b0) to "01" in software with CNVSS connected to VSS. This mode enables external memory expansion while maintaining the validity of the internal ROM. However, some I/O devices will not support the memory expansion mode. Internal ROM will take precedence over external memory if addresses conflict. (3) Microprocessor mode Select this mode by resetting the microcomputer with CNVSS connected to VCC, or by setting the processor mode bits to "10" in software with CNVSS connected to VSS. In microprocessor mode, the internal ROM is no longer valid and external memory must be used.
b7 b0
000016 000816
SFR area
000016 000816
SFR area
004016
internal RAM reserved area
004016
internal RAM reserved area
084016
084016
YYYY16
internal ROM
*
FFFF16
Memory expansion mode
FFFF16
Microprocessor mode
The shaded area are external memory area.
*: YYYY16 indicates the first address of internal ROM.
Fig. 61. Memory maps in various processor modes
CPU mode register (CPUM : address 003B16) Processor mode bits (CM1, CM0)
b1 b0
0 0 1 1
0: Single-chip mode 1: Memory expansion mode 0: Microprocessor mode 1: Not available
Stack page selection bit 0: 0 page 1: 1 page
Fig. 62. Structure of CPU mode register
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HARDWARE
FUNCTIONAL DESCRIPTION
Bus control at memory expansion _____ The 3807 group has a built-in ONW function to facilitate access to external (expanded) memory and I/O devices in memory expansion mode or microprocessor mode. _____ If an "L" level signal is input to port P32/ONW when the CPU is in a read or write state, the corresponding read or write cycle is extended ___ ___ by one cycle of . During this extended period, the RD or WR signal remains at "L". This extension function is valid only for writing to and reading from addresses 000016 to 000716 and 084016 to FFFF16, and only read and write cycles are extended.
Read cycle
Dummy cycle Write cycle
Read cycle Dummy cycle
Write cycle
AD15--AD0 RD WR ONW
*
*
*
* Period during which ONW input signal is received During this period, the ONW signal must be fixed at either "H" or "L". At all other times, the input level of the ONW signal has no affect on operations. The bus cycles is not extended for an address in the area 000816 to 083F16, regardless of whether the ONW signal is received.
_____
Fig. 63. ONW function timing
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NOTES ON PROGRAMMING
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1." After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) is at least on 500 kHz during an A-D _____ conversion. (When the ONW pin has been set to "L", the A-D conversion will take twice as long to match the longer bus cycle, and so f(XIN) must be at least 1 MHz.) Do not execute the STP or WIT instruction during an A-D conversion.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction.
D-A Converter
The accuracy of the D-A converter becomes rapidly poor under the VCC = 4.0 V or less condition; a supply voltage of VCC 4.0 V is recommended. When a D-A converter is not used, set all values of D-Ai conversion registers (i=1 to 4) to "0016."
Decimal Calculations
*To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. *In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock is half of the XIN frequency in high-speed mode. _____ When the ONW function is used in modes other than single-chip mode, the frequency of the internal clock may be one fourth of the XIN frequency.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
*The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. *The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The following cannot be used: *The data transfer instruction (LDA, etc.) *The operation instruction when the index X mode flag (T) is "1" *The addressing mode which uses the value of a direction register as an index *The bit-test instruction (BBC or BBS, etc.) to a direction register *The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY1 output enable bit to "1." Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. SOUT2 pin for serial I/O2 goes to high impedance after transfer is completed. When in serial I/O1 (clock-synchronous mode) or in serial I/O2 an external clock is used as synchronous clock, write transmission data to both the transmit buffer register and serial I/O2 register, during transfer clock is "H."
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NOTES ON USAGE
NOTES ON USAGE Handling of Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (Vss pin) and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F--0.1 F is recommended.
P34 clock output function
In the case of using an I/O port P34 as a clock output function, note the following : when an output clock frequency is changed during outputting a clock, the port may feed a noise having a shorter pulse width than the standard at the switch timing. Besides, it also may happen at the timing for switching the low-speed mode to the middle/ high-speed mode.
Timer X and timer Y
In the pulse period measurement mode or the pulse width measurement mode for timers X and Y, set the "L" or "H" pulse width of input signal from CNTR0/CNTR1 pin to 2 cycles or more of a timer count source.
EPROM version/One Time PROM version
The CNVSS pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVSS pin and VSS pin or VCC pin with 1 to 10 k resistance. The mask ROM version track of port CNVSS has no operational interference even if it is connected via a resistor.
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DATA REQUIRED FOR MASK ORDERS/ROM PROGRAMMING METHOD
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies)
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-in EPROM version can be read or programmed with a general purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table. 10. Special programming adapter Package 80P6N-A 80D0 Name of Programming Adapter PCA4738F-80A PCA4738L-80A
The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 64 is recommended to verify programming.
Programming with PROM programmer
Screening (Caution) (150C for 40 hours)
Verification with PROM programmer
Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours.
Fig. 64. Programming and testing of One Time PROM version
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HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
Interrupt 3807 group permits interrupts on the basis of 16 sources. It is vector interrupts with a fixed priority system. Accordingly, when two or more interrupt
requests occur during the same sampling, the higherpriority interrupt is accepted first. This priority is determined by hardware, but variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. For interrupt sources, vector addresses and interrupt priority, refer to "Table 11."
Table 11. Interrupt sources, vector addresses and interrupt priority Vector addresses Priority 1 2 3 4 5 6 7 8 Interrupt sources High-order Low-order Reset (Note) INT0 interrupt INT1 interrupt Serial I/O1 receive interrupt Serial I/O1 transmit interrupt Timer X interrupt Timer Y interrupt INT3 interrupt Timer 2 interrupt INT4 interrupt Timer 3 interrupt CNTR0 interrupt CNTR1 interrupt Serial I/O2 interrupt INT2 interrupt Timer 1 interrupt Timer A interrupt Timer B interrupt A-D conversion interrupt ADT interrupt FFFD16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFFC16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected Remarks
9
FFED16
FFEC16
10 11 12 13
FFEB16 FFE916 FFE716 FFE516
FFEA16 FFE816 FFE616 FFE416
External interrupt(active edge selectable) Valid when INT3 interrupt is selected Valid when timer 2 interrupt is selected External interrupt(active edge selectable) Valid when INT4 interrupt is selected Valid when timer 3 interrupt is selected External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O2 is selected External interrupt(active edge selectable) Valid when INT2 interrupt is selected Valid when timer 1 interrupt is selected
14 15 16
FFE316 FFE116 FFDF16
FFE216 FFE016 FFDE16
17
BRK instruction interrupt
FFDD16
FFDC16
Valid when A-D interrupt is selected External interrupt(only at falling edge) Valid when ADT interrupt and A-D external trigger valid are selected Non-maskable software interrupt
Note: Reset functions in the same way as an interrupt with the highest priority.
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FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution. Figure 65 shows a timing chart after an interrupt occurs, and Figure 66 shows the time up to execution of the interrupt processing routine.
SYNC RD WR Address bus Data bus
SYNC BL, BH AL, AH SPS
PC Not used
S, SPS
S-1, SPS S-2, SPS
BL AL
BH
AL, AH AH
PCH PCL
PS
: CPU operation code fetch cycle : Vector address of each interrupt : Jump destination address of each interrupt : "0016" or "0116"
Fig. 65 Timing chart after an interrupt occurs
Generation of interrupt request
Start of interrupt processing
Main routine
Waiting time for post-processing of pipeline
Stack push and Vector fetch
Interrupt processing routine
0 to 16 T cycles
2 cycles
5 cycles
7 to 23 cycles (At performing 8.0 MHz, 1.75 s to 5.75 s) T : at execution of DIV instruction (16 cycles) Fig. 66 Time up to execution of the interrupt processing routine
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HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
A-D Converter A-D conversion is started by setting AD conversion completion bit to "0." During A-D conversion, internal operations are performed as follows. 1. After the start of A-D conversion, A-D conversion register goes to "0016." 2. The highest-order bit of A-D conversion register is set to "1," and the comparison voltage Vref is input to the comparator. Then, Vref is compared with analog input voltage VIN. 3. As a result of comparison, when Vref < VIN, the highest-order bit of A-D conversion register be comes "1." When Vref > VIN, the highest-order bit becomes "0." By repeating the above operations up to the lowestorder bit of the A-D conversion register, an analog value converts into a digital value. A-D conversion completes at 50 clock cycles (12.5 s at f(XIN) = 8.0 MHz) after it is started, and the result of the conversion is stored into the A-D conversion register. Concurrently with the completion of A-D conversion, A-D conversion interrupt request occurs, so that the AD conversion interrupt request bit is set to "1."
Relative formula for a reference voltage VREF of A-D converter and Vref When n = 0 When n = 1 to 255 Vref = 0 Vref = VREF ! (n - 0.5) 256 n : the value of A-D converter (decimal numeral)
Table 12. Change of A-D conversion register during A-D conversion Change of A-D conversion register At start of conversion First comparison Second comparison Third comparison
V
Value of comparison voltage (Vref) 0 VREF 2 VREF 2 VREF 2 - VREF 512 VREF - VREF VREF 512 512 VREF 8
0 1 1 1
V
0 0 1 2
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
V
4 VREF 4
-
After completion of eighth comparison V1: V3: V5: V7: A A A A result result result result of of of of the the the the
A result of A-D conversion
V
1
V
2
V
3
V
4
V
5 A A A A
V
6
V
7
V
8 the the the the second comparison fourth comparison sixth comparison eighth comparison
first comparison third comparison fifth comparison seventh comparison
V2: V4: V6: V8:
result result result result
of of of of
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FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 67 shows A-D conversion equivalent circuit, and Figure 68 shows A-D conversion timing chart.
VCC
VSS VIN Sampling clock
VCC AVSS
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12
b5 b3 b2 b1 b0
C Chopper amplifier
A-D conversion register
A-D control register ADVREF
Build-in D-A converter
Vref
Reference clock
ADT/A-D conversion interrupt request
AVSS Fig. 67 A-D conversion equivalent circuit
Write signal for A-D control register
50 cycles
AD conversion completion bit
Sampling clock
Fig. 68 A-D conversion timing chart
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CHAPTER 2 APPLICATION
2.1 2.2 2.3 2.4 2.5 2.6 2.7 I/O port Timer Serial I/O Real time output port A-D converter Reset Application circuit example
APPLICATION
2.1 I/O port
2.1 I/O port
2.1.1 Memory map of I/O port
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D)
Fig. 2.1.1 Memory map of I/O port related registers
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2.1 I/O port
2.1.2 Related registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 7, 8) [Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0E16, 1016]
B 0 Port Pi0 1 Port Pi1
Name
q
Function
In output mode Write Port latch Read In input mode Write : Port latch Read : Value of pins
At reset
RW
0 0 0 0 0 0 0 0
q
2 Port Pi2 3 Port Pi3 4 Port Pi4 5 Port Pi5 6 Port Pi6 7 Port Pi7
Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 7, 8)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 7, 8) [Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0F16, 1116]
B
Name
Function
0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode
At reset
RW
! ! ! ! ! ! ! !
0 Port Pi direction register 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 7, 8)
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APPLICATION
2.1 I/O port
Port P6
b7 b6 b5 b4 b3 b2 b1 b0 Port P6 (P6) [Address : 0C16]
B 0 Port P60 1 Port P61
Name
q
Function
In output mode Write Port latch Read In input mode Write : Port latch Read : Value of pins
At reset
RW
0 0 0 0 0 0 0 0 ! ! ! !
q
2 Port P62 3 Port P63 4 Port P64 5 Port P65
(Note) (Note)
6 Nothing is allocated for these bits. These are write disabled bits. 7 When these bits are read out, the values are "0".
Note : These bits are used only for input port.
Fig. 2.1.4 Structure of Port P6
Port P6 direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port P6 direction register (P6D) [Address : 0D16]
B
registers
Name
Function
0 : Port P60 input mode 1 : Port P60 output mode 0 : Port P61 input mode 1 : Port P61 output mode 0 : Port P62 input mode 1 : Port P62 output mode
At reset
RW
! ! ! ! ! ! ! !
0 Port P60--P62 direction 1 2
0 0 0 0 0 0 0 0
3 Ports P63 and P64 are input ports.
Accordingly, these bits do not have a direction register. 4 Nothing is allocated for these bits. 0 : Port P65 input mode 1 : Port P65 output mode 6 Nothing is allocated for these bits. These are write disabled bits. 7 When these bits are read out, the values are "0".
5 Port P65 direction register
Fig. 2.1.5 Structure of Port P6 direction register
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APPLICATION
2.1 I/O port
2.1.3 Handling of unused pins Table 2.1.1 Handling of unused pins (in single-chip mode) Name of Pins/Ports P0, P1, P2, P3, P4, P5, P6, P7, P8 Handling * Set to the input mode and connect to VCC or VSS through a resistor of 1 k to 10 k . * Set to the output mode and open at "L" or "H." Connect to VSS(GND) or open. Connect to VSS(GND). Connect to VSS(GND). Open Open (only when using external clock).
ADVREF AVSS CMPVCC CMPOUT XOUT
Table 2.1.2 Handling of unused pins (in memory expansion mode and microprocessor mode) Name of Pins/Ports P30, P31 P4, P5, P6, P7, P8 Handling Open * Set to the input mode and connect to VCC or VSS through a resistor of 1 k to 10 k . * Set to the output mode and open at "L" or "H." Connect to VSS(GND) or open. Connect to VCC through a resistor of 1 k to 10 k . Open Open Open Connect to VSS(GND). Connect to VSS(GND). Open Open (only when using external clock).
ADVREF
____
ONW
_________
RESETOUT
SYNC AVSS CMPVCC CMPOUT XOUT
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APPLICATION
2.2 Timer
2.2 Timer
2.2.1 Memory map of timer
001416 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 003A16 003C16 003D16 003E16 003F16
Timer XY control register (TXYCON) Timer X Low-order (TXL) Timer X High-order (TXH) Timer Y Low-order (TYL) Timer Y High-order (TYH) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer X mode register (TXM) Timer Y mode register (TYM) Timer 123 mode register (T123M) Interrupt edge selection register (INTEDGE) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
Fig. 2.2.1 Memory map of timer related registers
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2.2 Timer
2.2.2 Related registers
Timer XY control register
b7 b6 b5 b4 b3 b2 b1 b0 Timer XY control register (TXYCON) [Address : 1416]
B 0 1
Name
Timer X stop control bit Timer Y stop control bit
Function
0 : Start counting 1 : Stop counting
At reset
RW
1 1 0 0 0 0 0 0
! ! ! ! ! !
0 : Start counting 1 : Stop counting 2 Nothing is allocated for these bits. These are write disabled bits. 3 When these bits are read out, the values are "0."
4 5 6 7
Fig. 2.2.2 Structure of Timer XY control register
Timer X Low-order, Timer X High-order, Timer Y Low-order, Timer Y High-order
b7 b6 b5 b4 b3 b2 b1 b0 Timer X Low-order (TXL), Timer X High-order (TXH) [Address : 2016 , 2116] Timer Y Low-order (TYL), Timer Y High-order (TYH) [Address : 2216 , 2316]
B 0 1 2
q q q
Function
A count value of each timer is set. At writing q A value set in this register is written to both a Timer and a corresponding Timer latch at the same time, or to only a Timer latch. q A value is written to low-order first. At reading q When this register is read out, a value (count value) of a corresponding Timer is read out. q A measurement value is read out in pulse period measurement mode and pulse width measurement mode. q A value is read out from high-order first.
At reset
RW
1 1 1 1 1 1 1 1
3 4 5 6 7
Fig. 2.2.3 Structure of Timer X Low-order, Timer X High-order, Timer Y Low-order, Timer Y High-order
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APPLICATION
2.2 Timer
Timer 1, Timer 3
b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 (T1), Timer 3 (T3) [Address : 2416, 2616]
B 0 1 2 3 4 5 6 7
Function
q q q
At reset
RW
A count value of each Timer is set. A value set in this register is written to both each Timer and a corresponding Timer latch at the same time. When this register is read out, a value (count value) of a corresponding Timer is read out.
1 1 1 1 1 1 1 1
Fig. 2.2.4 Structure of Timer 1, Timer 3
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2) [Address : 2516]
B 0 1 2 3 4 5 6 7
Function
q q
At reset
RW
q
A count value of Timer 2 is set. A value set in this register is written to both Timer 2 and a corresponding Timer 2 latch at the same time, or to only Timer 2 latch. When this register is read out, a value (count value) of a corresponding Timer 2 is read out.
1 0 0 0 0 0 0 0
Fig. 2.2.5 Structure of Timer 2
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2.2 Timer
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TXM) [Address : 2716]
B 0
Name
Timer X operating mode bits
b2 b1 b0
Function
0 : Timer * Event counter mode 1 : Pulse output mode 0 : Pulse period measurement mode 1 : Pulse width measurement mode 0 : Programmable waveform generation mode 1 0 1 : Programmable one-shot generation mode 1 1 0 : PWM mode 1 1 1 : Not available 0 : To a latch and a timer at the same time 1 : To only latch 0 : "L" output 1 : "H" output It depends on the operating mode of the Timer X (refer to Table 2.2.1). 0: 1: 0: 1:
b6
At reset
RW
1
0 0 0 0 1
0 0 1 1 0
0
0
2 3 4 5
Timer X write control bit Output level latch CNTR0 active edge switch bit
0 0 0 0 0 0
b7 Timer X count source selection 0 0 1 7 1
6 bits
f(XIN)/2 f(XIN)/16 f(XCIN) Input signal from CNTR0 pin
Fig. 2.2.6 Structure of Timer X mode register
Timer Y mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer Y mode register (TYM) [Address : 2816]
B 0
Name
Timer Y operating mode bits
b2 b1 b0
Function
0 : Timer * Event counter mode 1 : Pulse output mode 0 : Pulse period measurement mode 1 : Pulse width measurement mode 0 : Programmable waveform generation mode 1 0 1 : Programmable one-shot generation mode 1 1 0 : PWM mode 1 1 1 : Not available 0 : To a latch and a timer at the same time 1 : To only latch 0 : "L" output 1 : "H" output It depends on the operating mode of the Timer Y (refer to Table 2.2.1). 0: 1: 0: 1:
b6
At reset
RW
1
0 0 0 0 1
0 0 1 1 0
0
0
2 3 4 5
Timer Y write control bit Output level latch CNTR1 active edge switch bit
0 0 0 0 0 0
b7 Timer Y count source selection 0 0 1 7 1
6 bits
f(XIN)/2 f(XIN)/16 f(XCIN) Input signal from CNTR1 pin
Fig. 2.2.7 Structure of Timer Y mode register
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APPLICATION
2.2 Timer
Table. 2.2.1 Function of CNTR0/CNTR1 active edge switch bit Operating mode of Timer X/Timer Y Timer mode Function of CNTR0/CNTR1 edge switch bit (bit 5 of each address 2716 and 2816) Generation of CNTR0/CNTR1 interrupt request : Falling edge (No effect on timer count) Generation of CNTR0/CNTR1 interrupt request : Rising edge (No effect on timer count) Timer X/Timer Y : Count at rising edge Generation of CNTR0/CNTR1 interrupt request : Falling edge Timer X/Timer Y : Count at falling edge Generation of CNTR0/CNTR1 interrupt request : Rising edge Start of pulse output : From "H" level Generation of CNTR0/CNTR1 interrupt request : Falling edge Start of pulse output : From "L" level Generation of CNTR0/CNTR1 interrupt request : Rising edge Timer X/Timer Y : Measurement of a period between a falling edge and the next falling edge Generation of CNTR0/CNTR1 interrupt request : Falling edge Timer X/Timer Y : Measurement of a period between a rising edge and the next rising edge Generation of CNTR0/CNTR1 interrupt request : Rising edge Timer X/Timer Y : Measurement of "H" level width Generation of CNTR0/CNTR1 interrupt request : Falling edge Timer X/Timer Y : Measurement of "L" level width Generation of CNTR0/CNTR1 interrupt request : Rising edge Timer X/Timer Y : Start of a pulse output at "L" level, and output of an one-shot "H" level pulse Generation of CNTR0/CNTR1 interrupt request : Falling edge Timer X/Timer Y : Start of a pulse output at "H" level, and output of an one-shot "L" level pulse Generation of CNTR0/CNTR1 interrupt request : Rising edge
"0" "1"
* * * * * * * * * * * * *
Event counter mode
"0" "1"
Pulse output mode
"0" "1"
Pulse period measurement mode "0"
"1" Pulse width measurement mode * * * * * * * * "1" *
"0" "1"
Programmable one-shot generation mode
"0"
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2.2 Timer
Timer 123 mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 123 mode register (T123M) [Address : 2916]
B
Name
Function
At reset
RW
TOUT output active edge switch 0 : Start at outputting "H" signal 0 bit 1 : Start at outputting "L" signal 0 : Disabled TOUT output 1 : Enabled TOUT output Timer 2 write control bit 0 : To a latch and a timer at the same time 2 1 : To only latch 0 : Output signal from Timer 1 Timer 2 count source selection 3 bit 1 : f(XIN)/16 (Note 1)
0 0 0 0 0 0 0 0
!
1
TOUT output control bit
Timer 3 count source selection 0 : Output signal from Timer 1 1 : f(XIN)/16 (Note 1) b6 b5 Timer 1 count source selection 0 0 : f(XIN)/16 (Note 1) 5 bit 0 1 : f(XIN)/2 (Note 2)
4 bit
1 0 : f(XCIN) 1 1 : Not available Nothing is allocated for this bit. It is a write disabled bit. 7 When this bit is read out, the value is "0." Note 1 : In low-speed mode f(XCIN)/16 is selected. 2 : In low-speed mode f(XCIN)/2 is selected.
6
Fig. 2.2.8 Structure of Timer 123 mode register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address : 3A16]
B
Name
Function
0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active
At reset
RW
INT0 interrupt edge selection 0 bit INT1 interrupt edge selection 1 bit INT2 interrupt edge selection 2 bit
0 0 0 0 0 0 0 0
3 bit 4 bit
INT3 interrupt edge selection INT4 interrupt edge selection
0 : Falling edge active 1 : Rising edge active Timer 1/INT2 interrupt sources 0 : INT2 interrupt 5 bit 1 : Timer 1 interrupt Timer 2/INT3 interrupt sources 0 : INT3 interrupt 6 bit 1 : Timer 2 interrupt
7 bit
Timer 3/INT4 interrupt sources 0 : INT4 interrupt 1 : Timer 3 interrupt
Fig. 2.2.9 Structure of Interrupt edge selection register
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APPLICATION
2.2 Timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C16]
B 0 1
Name
INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt Serial I/O1 transmit interrupt Timer X interrupt request bit
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T T T
0 0 0 0 0 0 0 0
2 request bit
3 request bit 4
0 : No interrupt request 1 : Interrupt request Timer Y interrupt request bit 0 : No interrupt request 5 1 : Interrupt request Timer 2/INT3 interrupt request 0 : No interrupt request 6 bit 1 : Interrupt request
7 bit
Timer 3/INT4 interrupt request 0 : No interrupt request 1 : Interrupt request
T "0" is set by software, but not "1."
Fig. 2.2.10 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address : 3D16]
B 0 1
Name
CNTR0 interrupt request bit CNTR1 interrupt request bit
Function
0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T T !
0 0 0 0 0 0 0 0
0 : No interrupt request 1 : Interrupt request Serial I/O2 interrupt request 0 : No interrupt request 2 bit 1 : Interrupt request Timer 1/INT2 interrupt request 0 : No interrupt request 3 1 : Interrupt request bit 0 : No interrupt request 1 : Interrupt request Timer B interrupt request bit 0 : No interrupt request 5 1 : Interrupt request ADT/AD conversion interrupt 0 : No interrupt request 6 request bit 1 : Interrupt request Nothing is allocated for this bit. It is a write disabled bit. 7 When this bit is read out, the value is "0."
4
Timer A interrupt request bit
T "0" is set by software, but not "1."
Fig. 2.2.11 Structure of Interrupt request register 2
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3807 GROUP USER'S MANUAL
APPLICATION
2.2 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E16]
B 0 1
Name
INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt Serial I/O1 transmit interrupt Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2/INT3 interrupt enable Timer 3/INT4 interrupt enable
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 0 0 0 0 0 0 0
2 enable bit
3 enable bit 4 5
6 bit 7 bit
Fig. 2.2.12 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2) [Address : 3F16]
B 0 1
Name
CNTR0 interrupt enable bit CNTR1 interrupt enable bit Serial I/O2 interrupt enable Timer 1/INT2 interrupt enable bit Timer A interrupt enable bit Timer B interrupt enable bit ADT/AD conversion interrupt
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 0 0 0 0 0 0 0
2 bit 3 4 5
6 enable bit 7
Fix this bit to "0."
Fig. 2.2.13 Structure of Interrupt control register 2
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APPLICATION
2.2 Timer
2.2.3 Timer application examples (1) Basic functions and uses [Function 1] Control of Event interval (Timer X, Timer Y, Timer 1, Timer 2, Timer 3) The Timer count stop bit is set to "0" after setting a count value to a timer. Then a timer interrupt request occurs after a certain period. [Use] * Generation of an output signal timing * Generation of a waiting time [Function 2] Control of Cyclic operation (Timer X, Timer Y, Timer 1, Timer 2, Timer 3) The value of a timer latch is automatically written to a corresponding timer every time a timer underflows, and each cyclic timer interrupt request occurs. [Use] * Generation of cyclic interrupts * Clock function (measurement of 25m second) * Control of a main routine cycle
Application example 1
[Function 3] Output of Rectangular waveform (Timer X, Timer Y, Timer 2) The output level of the CNTR pin is inverted every time a timer underflows (Pulse output mode). [Use] * A piezoelectric buzzer output Application example 2 * Generation of the remote-control carrier waveforms [Function 4] Count of External pulse (Timer X, Timer Y) External pulses input to the CNTR pin are selected as a timer count source (Event counter mode). [Use] * Measurement of frequency Application example 3 * Division of external pulses. * Generation of interrupts in a cycle based on an external pulse. (count of a reel pulse) [Function 5] Measurement of External pulse width (Timer X, Timer Y) The "H" or "L" level width of external pulses input to CNTR pin is measured (Pulse width measurement mode). [Use] * Measurement of external pulse frequency (Measurement of pulse width of FG pulse V generated by motor) Application example 4 * Measurement of external pulse duty (when the frequency is fixed)
VFG pulse : Pulse used for detecting the motor speed to control the motor speed.
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APPLICATION
2.2 Timer
(2) Timer application example 1 : Clock function (measurement of 25 ms) Outline : The input clock is divided by a timer so that the clock counts up every 25 ms. Specifications : * The clock f(XIN) = 8 MHz is divided by a timer. * The clock is counted at intervals of 25 ms by the Timer 3 interrupt. Figure 2.2.14 shows a connection of timers and a setting of division ratios, Figures 2.2.15 show a setting of related registers, and Figure 2.2.16 shows a control procedure.
Fixed
Timer 1
Timer 3
Timer 3 interrupt request bit The clock is divided by 40 by software.
f(XIN) = 8 MHz
1/16
1/250
1/50
0 or 1
25 ms
1/40
1 second
0 : No interrupt request 1 : Interrupt request
Fig. 2.2.14 Connection of timers and setting of division ratios [Clock function]
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APPLICATION
2.2 Timer
Timer 123 mode register (Address : 2916)
b7 b0
T123M
000
Timer 3 count source selection bit : Output signal from Timer 1 Timer 1 count source selection bits : f(XIN)/16
Timer 1 (Address : 2416)
b7 b0
T1
b7
249 Timer 3 (Address : 2616)
b0
Set "division ratio - 1"
T3
49
Interrupt edge selection register (Address : 3A16)
b7 b0
INTEDGE
1
Timer 3/INT4 interrupt sources bit : Timer 3 interrupt
Interrupt control register 1 (Address : 3E16)
b7 b0
ICON1
1
Timer 3/INT4 interrupt enable bit : Interrupt enabled
Interrupt request register 1 (Address : 3C16)
b7 b0
IREQ1
0
Timer 3/INT4 interrupt request bit (becomes "1" every 25 ms)
Fig. 2.2.15 Setting of related registers [Clock function]
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APPLICATION
2.2 Timer
Control procedure : Figure 2.2.16 shows a control procedure.
RESET
q
X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
Initialization SEI T123M (Address : 2916) X000XXXX2 INTEDGE (Address : 3A16), bit7 1 ICON1 (Address : 3E16), bit7 1 T1 T3 CLI
.... ....
[Processing for completion of setting clock] (Note 1)
q
All interrupts : Disabled Select each count source of the Timer 1 and Timer 3. Timer 3 interrupt : Enabled Set "division ratio - 1" to the Timer 1 and Timer 3. Interrupts : Enabled
Fig. 2.2.16 Control procedure [Clock function]
....
q q
....
(Address : 2416) (Address : 2616)
250 - 1 50 - 1
q
q
Main processing
(Address : 2416) T1 (Address : 2616) T3 IREQ1 (Address : 3C16), bit7
250 - 1 50 - 1 0
q
q
When restarting the clock from zero second after completing to set the clock, reset timers. Set the Timer 3 interrupt request bit to "0."
Note 1: This processing is performed only at completing to set the clock.
Timer 3 interrupt processing routine
CLT (Note 2) CLD (Note 3) Push register to stack
Note 2: When using the Index X mode flag (T). Note 3: When using the Decimal mode flag (D).
q
Push the register used in the interrupt processing routine into the stack.
Clock stop? N Clock count up (1/40 second-year)
Y
q
Check if the clock has already been set.
q
Count up the clock.
Pop registers
q
Pop registers which is pushed to stack
RTI
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APPLICATION
2.2 Timer
(3) Timer application example 2 : Piezoelectric buzzer output Outline : The rectangular waveform output function of a timer is applied for a piezoelectric buzzer output. Specifications : * The rectangular waveform resulting from dividing clock f(XIN) = 8 MHz into about 2 kHz (2049 Hz) is output from the P54/CNTR0 pin. * The level of the P54/CNTR0 pin fixes to "H" while a piezoelectric buzzer output is stopped. Figure 2.2.17 shows an example of a peripheral circuit, and Figure 2.2.18 shows a connection of the timer and setting of the division ratio.
The "H" level is output while a piezoelectric buzzer output is stopped. CNTR0 output
3807 group
P54/CNTR0 PiPiPi.... 244 s 244 s Set a division ratio so that the underflow output cycle of the Timer X becomes this value.
Fig. 2.2.17 Example of a peripheral circuit
Timer X count source selection bit f(XIN) = 8 MHz
Timer X
1/16
1/122
CNTR0
Fig. 2.2.18 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output]
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APPLICATION
2.2 Timer
Timer X mode register (Address : 2716)
b7 b0
TXM
010
0001
Timer X operating mode bits : Pulse output mode Timer X write control bit : Write to a latch and a timer at the same time. CNTR0 active edge switch bit : Output from the "H" level Timer X count source selection bits : f(XIN)/16
Timer XY control register (Address : 1416)
b7 b0
TXYCON
1
Timer X stop control bit : Stop counting (set this bit to "0" at starting counting.)
Timer X High-order (Address : 2116)
b7 b0
TXH
b7
0 Timer X Low-order (Address : 2016)
b0
Set "division ratio - 1"
TXL
122--1
Port P5 direction register (Address : 0B16)
b7 b0
P5D
1
P54/CNTR0 : Output mode
Port P5 (Address : 0A16)
b7 b0
P5
1
"H" is output at stopping a piezoelectric buzzer output.
Fig. 2.2.19 Setting of related registers [Piezoelectric buzzer output]
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APPLICATION
2.2 Timer
Control procedure : Figure 2.2.20 shows a control procedure.
RESET
qX
Initialization P5 P5D
: This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
0 ICON1 (Address : 3E16), bit4 1 TXYCON(Address : 1416), bit0 TXM (Address : 2716) 010X00012 TXL (Address : 2016) 122 - 1 TXH (Address : 2116) 0
Output unit
During stopping outputting a piezoelectric buzzer
Fig. 2.2.20 Control procedure [Piezoelectric buzzer output]
.... ....
1 (Address : 0A16), bit4 (Address : 0B16) XXX1XXXX2
q
Set the port state at stopping a piezoelectric buzzer output. ("H" level output) Timer X interrupts : Disabled Timer X count : Stopped (stop outputting a piezoelectric buzzer). Timer X : Pulse output mode Set "division ratio - 1" to the Timer X.
q
q
q
q
Main processing The piezoelectric buzzer request occured in the main processing is processed in the output unit.
q
A piezoelectric buzzer is requested? N
Y
TXYCON (Address : 1416), bit0
1
TXYCON (Address : 1416), bit0
0
During outputting a piezoelectric buzzer
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3807 GROUP USER'S MANUAL
APPLICATION
2.2 Timer
(4) Timer application example 3 : Measurement of frequency Outline : The following two values are compared for judging if the frequency is within a certain range. * A value counted a pulse which is input to P55/CNTR1 pin by a timer. * A referance value Specifications : * The pulse is input to the P55/CNTR1 pin and counted by the Timer Y. * A count value is read out at the interval of about 2 ms (Timer X interrupt interval). When the count value is 28 to 40, it is regarded the input pulse as a valid. * Because the timer is a down-counter, the count value is compared with 227 to 215 . 227 to 215 = 255 (initialized value of counter) - 28 to 40 (the number of valid value). Figure 2.2.21 shows a method for judging if input pulse exists, and Figure 2.2.22 and Figure 2.2.23 show a setting of related registers.
Input pulse
****
****
****
71.4 s or more (14 kHz or less) Invalid
71.4 s (14 kHz) Valid
50 s (20 kHz)
50 s or less (20 kHz or more) Invalid
2 ms = 28 counts 71.4 s
2 ms 50 s
= 40 counts
Fig 2.2.21 A method for judging if input pulse exists
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APPLICATION
2.2 Timer
Timer Y mode register (Address : 2816)
b7 b0
TYM
111
0000
Timer Y operating mode bits : Timer*Event counter mode Timer Y write control bit : Write to a latch and a timer at the same time. CNTR1 active edge switch bit : Count at falling edge Timer Y count source selection bits : Input signal from CNTR1 pin
Timer X mode register (Address : 2716)
b7 b0
TXM
01
0000
Timer X operating mode bits : Timer*Event counter mode Timer X write control bit : Write to a latch and a timer at the same time. Timer X count source selection bits : f(XIN)/16
Timer XY control register (Address : 1416)
b7 b0
TXYCON
11
Timer X stop control bit : Stop counting (set this bit to "0" at starting counting.) Timer Y stop control bit : Stop counting (set this bit to "0" at starting counting.)
Timer Y High-order (Address : 2316)
b7 b0
TYH
b7
0016 Timer Y Low-order (Address : 2216)
b0
Set to "FF16" before counting a pulse. (After a certain time, a number of inputted pulse is decremented from this value.)
TYL
FF16
Timer X High-order (Address : 2116)
b7 b0
TXH
b7
0316 Timer X Low-order (Address : 2016)
b0
Set "division ratio - 1" for making underflow every 2 ms input at inputting f(XIN)=8MHz.
TXL
E716
Fig. 2.2.22 Setting of related registers (1) [Measurement of frequency]
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APPLICATION
2.2 Timer
Interrupt control register 1 (Address : 3E16)
b7 b0
ICON1
01
Timer X interrupt enable bit : Interrupt enabled Timer Y interrupt enable bit : Interrupt disabled
Interrupt request register 1 (Address : 3C16)
b7 b0
IREQ1
0
Timer X interrupt request bit (becomes "1" every 2 ms)
Port P5 direction register (Address : 0B16)
b7 b0
P5D
0
P55/CNTR1 : Input mode
Fig. 2.2.23 Setting of related registers (2) [Measurement of frequency]
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APPLICATION
2.2 Timer
Control procedure : Figure 2.2.24 shows a control procedure.
RESET Initialization SEI (Address : 2816) 111X00002 TYM (Address : 0B16) XX0XXXXX2 P5D XXXXXX112 TXYCON(Address : 1416) (Address : 2216) FF16 TYL (Address : 2316) 0016 TYH (Address : 2716) 01XX00002 TXM (Address : 2016) E716 TXL (Address : 2116) 0316 TXH 0 ICON1 (Address : 3E16), bit5 1 ICON1 (Address : 3E16), bit4 0 IREQ1 (Address : 3C16), bit4 TXYCON(Address : 1416) CLI
q X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
q
All interrupts : Disabled
0016
Fig. 2.2.24 Control procedure [Measurement of frequency] 2-24
3807 GROUP USER'S MANUAL
....
q
q
q q q
q q q
Timer Y : Timer*Event counter mode (Count at falling edge of pulse input from CNTR1 pin) Timer X count and Timer Y count :Stopped counting Timer X : Timer mode Timer X count source selection bit : f(XIN)/16 Set the division ratio so that the Timer X interrupt occurs every 2 ms. Timer Y interrupt : Disabled Timer X interrupt : Enabled Set the Timer X interrupt request bit to "0." Timer X count and Timer Y count :Started counting Interrupts : Enabled
....
XXXXXX002
q
....
q
~ ~
Timer X interrupt processing routine CLT (Note 1) CLD (Note 2) Push register to stack Note 1: When using the Index X mode flag (T). Note 2: When using the Decimal mode flag (D).
q
Push the register used in the interrupt processing routine into the stack When the count value is 256 or more, the processing is performed as out of range.
q
TYH (Address : 2316)? =0016
q
(A)
TYL (Address : 2216)
q
Read the count value. Store the count value in the accumulator (A).
D616
< (A) < E416?
Out of range
In range
q
q
Compare the count value read with the reference value. Store the comparison result in flag Fpulse. 1
Fpulse
0
Fpulse
TYL TYH
(Address : 2216) (Address : 2316)
FF16 0016
q
Initialize the count value
Processing for a result of judgment
Pop registers RTI
q
Pop registers which is pushed to stack.
APPLICATION
2.2 Timer
(5) Timer application example 4 : Measurement of pulse width of FG pulse generated by motor Outline : The "H" level width of a pulse input to the P54/CNTR0 pin is counted by Timer X. An underflow is detected by Timer X interrupt and an end of the input pulse "H" level is detected by CNTR0 interrupt. Specifications : * The "H" level width of FG pulse input to the P54/CNTR0 pin is counted by Timer X. (Example : When the clock frequency is 8 MHz, the count source would be 2 s that is obtained by dividing the clock frequency by 16. Measurement can be made up to 131.072 ms in the range of FFFF16 to 000016.) Figure 2.2.25 shows a connection of the timer and setting of the division ratio, and Figure 2.2.26 shows a setting of related registers.
Timer X count source selection bit f(XIN) = 8 MHz
Timer X
Timer X interrupt request bit
1/16
1/65536
0 or 1
131.072 ms
0 : No interrupt request 1 : Interrupt request
Fig. 2.2.25 Connection of the timer and setting of the division ratio [Measurement of pulse width]
3807 GROUP USER'S MANUAL
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APPLICATION
2.2 Timer
Timer X mode register (Address : 2716)
b7 b0
TXM
010
0011
Timer X operating mode bits : Pulse width measurement mode Timer X write control bit : Write to a latch and a timer at the same time. CNTR0 active edge switch bit : Measure the "H" level width Timer X count source selection bits : f(XIN)/16
Timer XY control register (Address : 1416)
b7 b0
TXYCON
1
Timer X stop control bit : Stop counting (set this bit to "0" at starting counting.)
Timer X High-order (Address : 2116)
b7 b0
TXH
b7
FF16 Timer X Low-order (Address : 2016)
b0
Set "FFFF16" before starting measuring a pulse width.
TXL
FF16 Interrupt control register 1 (Address : 3E16)
b7 b0
ICON1
1
Timer X interrupt enable bit : Interrupt enabled
Interrupt request register 1 (Address : 3C16)
b7 b0
IREQ1
0
Timer X interrupt request bit (This bit is set to "1" at underflow of Timer X.)
Interrupt control register 2 (Address : 3F16)
b7 b0
ICON2
1
CNTR0 interrupt enable bit : Interrupt enabled
Interrupt request register 2 (Address : 3D16)
b7 b0
IREQ2
0
CNTR0 interrupt request bit (This bit is set to "1" at completion of inputting "H" level signal.)
Port P5 direction register (Address : 0B16)
b7 b0
P5D
0
P54/CNTR0 : Input mode
Fig. 2.2.26 Setting of related registers [Measurement of pulse width] 2-26
3807 GROUP USER'S MANUAL
APPLICATION
2.2 Timer
Figure 2.2.27 and Figure 2.2.28 show a control procedure.
RESET Initialization SEI 010X00112 TXM (Address : 2716) P5D (Address : 0B16) XXX0XXXX2 TXYCON (Address : 1416), bit0 1 (Address : 2016) TXL 255 (Address : 2116) TXH 255 ICON1 (Address : 3E16), bit4 1 IREQ1 (Address : 3C16), bit4 0 ICON2 (Address : 3F16), bit0 1 IREQ2 (Address : 3D16), bit0 0 TXYCON (Address : 1416), bit0 0 CLI
q X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
q
All interrupts : Disabled Timer X : Pulse width measurement mode (Count "H" level width of pulse input from CNTR0 pin.) Timer X count : Stopped counting Set the initial value of the Timer X. Timer X interrupt : Enabled CNTR0 interrupt : Enabled Timer X count : Start Interrupts : Enabled
Timer X interrupt processing routine (Note) Processing for error RTI
q
Fig. 2.2.27 Control procedure (1) [Measurement of pulse width]
....
q q q q q q
....
q
~ ~
Error occurs
Note : The Timer X interrupt occurs at a level except a measurement level (when it is "L" level in this applicaion example). Process by software in accordance with the necessity like as a processing for errors is performed only at a measurement level (The CNTR0 input level is judged by reading a content of the Port P54 register).
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APPLICATION
2.2 Timer
CNTR0 interrupt processing routine (Note 1) CLT (Note 2) CLD (Note 3) Push register to stack
(A) Result of pulse width measurement high-order 8-bit (A) Result of pulse width measurement low-order 8-bit TXH (A) TXL (A)
q
Note 2: When using the Index X mode flag (T). Note 3: When using the Decimal mode flag (D). Push the register used in the interrupt processing routine into the stack. A count value is read out and stored to RAM.
q
Pop registers RTI
q
Pop registers which is pushed to stack.
Note 1: The first measurement value happen to be invalid at a start timing of the Timer X count as shown a following figure. Process it by software in accordance with the necessity. Example 1. Be started the Timer X count at "L" level of the CNTR0 input signal. (A level of the CNTR0 input signal is judged by reading a content of the Port P54 register.) 2. Be invalid the first CNTR0 interrupt after starting the Timer X count. [When the Timer X count is started at "L" level of the CNTR0 input signal]
000016 T2 T1
FFFF16
A value of T1 : Valid A value of T2 : Valid
CNTR0 input CNTR0 interrupt At starting counting the Timer X CNTR0 interrupt
[When the Timer X count is started at "H" level of the CNTR0 input signal]
000016 T1 T2
FFFF16
A value of T1 : Invalid
A value of T2 : Valid
CNTR0 input CNTR0 interrupt At starting counting the Timer X CNTR0 interrupt
Fig. 2.2.28 Control procedure (2) [Measurement of pulse width]
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APPLICATION
2.3 Serial I/O
2.3 Serial I/O
2.3.1 Memory map of serial I/O
001816 001916 001A16 001B16
Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON)
001C16 Baud rate generator (BRG) 001D16 Serial I/O2 control register 1 (SIO2CON1) 001E16 001F16 003A16 003C16 003D16 003E16 003F16
Serial I/O2 control register 2 (SIO2CON2) Serial I/O2 register (SIO2) Interrupt edge selection register (INTEDGE) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
Fig. 2.3.1 Memory map of serial I/O related registers
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APPLICATION
2.3 Serial I/O
2.3.2 Related registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 1816] B 0 1 2 3 4 5 6 7
Note : A content of the Transmit buffer register cannot be read out. A data cannot be written to the Receive buffer register.
Function
A transmission data is written to or a receive data is read out from this buffer register. * At writing : a data is written to the Transmit buffer register. * At reading : a content of the Receive buffer register is read out.
At reset
RW
? ? ? ? ? ? ? ?
Fig. 2.3.2 Structure of Transmit/Receive buffer register
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 status reigster (SIO1STS) [Address : 1916]
Name B Transmit buffer empty flag 0
(TBE)
Function
0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full 0 : Transmit shift in progress 1 : Transmit shift completed 0 : No error 1 : Overrun error 0 : No error 1 : Parity error 0 : No error 1 : Framing error 0 : (OE) (PE) (FE) = 0 1 : (OE) (PE) (FE) = 1
At reset
0 0 0 0 0 0 0 1
RW ! ! ! ! ! ! ! !
1 Receive buffer full flag (RBF) 2 Transmit shift register shift
completion flag (TSC)
3 Overrun error flag (OE) 4 Parity error flag (PE) 5 Framing error flag (FE) 6 Summing error flag (SE)
7 Nothing is allocated for this bit. It is a write disabled bit.
When this bit is read out, the value is "0."
Fig. 2.3.3 Structure of Serial I/O1 status register
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APPLICATION
2.3 Serial I/O
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 control register (SIO1CON) [Address : 1A16] B 0 1
Name
BRG count source selection bit (CSS) Serial I/O1 synchronous clock selection bit (SCS) 0 : f(XIN) 1 : f(XIN)/4
Function
(Note 1) (Note 2)
At reset
RW
0 0
At selecting clock synchronous serial I/O 0 : BRG output divided by 4 1 : External clock input
At selecting UART
0 : BRG output divided by 16 1 : External clock input divided by 16
2 3
SRDY1 output enable bit
(SRDY) Transmit interrupt source selection bit (TIC) Transmit enable bit (TE) Receive enable bit (RE) Serial I/O1 mode selection bit (SIOM) Serial I/O1 enable bit (SIOE)
4 5 6 7
0 : I/O port (P47) 1 : SRDY1 output pin 0 : Transmit buffer empty 1 : Transmit shift operating completion 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : UART 1 : Clock synchronous serial I/O
0 : Serial I/O1 disabled (P44-P47 : I/O port) 1 : Serial I/O1 enabled (P44-P47 : Serial I/O function pin)
0 0
0 0 0 0
Note 1 : In low-speed mode f(XCIN) is selected. 2 : In low-speed mode f(XCIN)/4 is selected.
Fig. 2.3.4 Structure of Serial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UARTCON) [Address : 1B16]
Name B Character length 0
selection bit (CHAS)
Function
0 : 8 bits 1 : 7 bits 0 : Parity checking disabled 1 : Parity checking enabled 0 : Even parity 1 : Odd parity 0 : 1 stop bit 1 : 2 stop bits In output mode 0 : CMOS output 1 : N-channel open-drain output
At reset
RW
0 0 0 0 0
1 Parity enable bit 2 3 4
5 6 7
(PARE) Parity selection bit (PARS) Stop bit length selection bit (STPS) P45/TxD P-channel output disable bit (POFF) Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "1."
1 1 1
! ! !
Fig. 2.3.5 Structure of UART control register
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2.3 Serial I/O
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator (BRG) [Address : 1C16]
B
Function
At reset
RW
0 A count value of Baud rate generator is set. 1 2 3 4 5 6 7
? ? ? ? ? ? ? ?
Fig. 2.3.6 Structure of Baud rate generator
Serial I/O2 control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 control register 1 (SIO2CON1) [Address : 1D16]
Name B 0 Internal synchronous
clock selection bits
Function
b2 b1 b0
At reset
RW
(Note) : : : : : : f(XIN)/8 f(XIN)/16 f(XIN)/32 f(XIN)/64 f(XIN)/128 f(XIN)/256 (f(XCIN)/8) (f(XCIN)/16) (f(XCIN)/32) (f(XCIN)/64) (f(XCIN)/128) (f(XCIN)/256)
0 0 0 0 0 0 0 0
1 2 3 Serial I/O2 port selection bit 4 5 6 7
0 0 0 0 1 1
0 0 1 1 1 1
0 1 0 1 0 1
0 : I/O port (P71, P72) 1 : SOUT2, SCLK2 output pin 0 : I/O port (P73) SRDY2 output enable bit 1 : SRDY2 output pin 0 : LSB first Transfer direction 1 : MSB first selection bit Serial I/O2 synchronous clock 0 : External clock 1 : Internal clock selection bit In output mode P71/ SOUT2, P72/ SCLK2 0 : CMOS output P-channel output disable bit 1 : N-channel open-drain output
Note : In low-speed mode ( ) is selected.
Fig. 2.3.7 Structure of Serial I/O2 control register 1
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2.3 Serial I/O
Serial I/O2 control register 2
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 control register 2 (SIO2CON2) [Address : 1E16]
Name B 0 Optional transfer bits 1 2
Function
b2 b1 b0
At reset
RW
1 1 1 0 0 0 0 0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 : 1 bit 1 : 2 bit 0 : 3 bit 1 : 4 bit 0 : 5 bit 1 : 6 bit 0 : 7 bit 1 : 8 bit
3 Nothing is allocated for these bits. These are write disabled bits. 4 When these bits are read out, the values are "0." 5 6 Serial I/O2 I/O comparative 0 : P51 I/O
signal control bit SOUT2 pin control bit (P71) 7 1 : SCMP2 output 0 : Output active 1 : Output high impedance
! ! !
Fig. 2.3.8 Structure of Serial I/O2 control register 2
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 register (SIO2) [Address : 1F16]
B
q
Function
At reset
RW
0 A shift register for serial transmission and reception.
At transmitting : Set a transmission data. q At receiving : Store a reception data. 1
? ? ? ? ? ? ? ?
2 3 4 5 6 7
Fig. 2.3.9 Structure of Serial I/O2 register
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2.3 Serial I/O
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address : 3A16]
Name B INT0 interrupt edge 0
selection bit
Function
0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : INT2 interrupt 1 : Timer 1 interrupt
At reset
RW
0 0 0 0 0 0 0 0
1 INT1 interrupt edge
selection bit 2 INT2 interrupt edge selection bit 3 INT3 interrupt edge selection bit
4 INT4 interrupt edge
selection bit 5 Timer 1/INT2 interrupt source bit Timer 2/INT3 interrupt 6 source bit
0 : INT3 interrupt 1 : Timer 2 interrupt
0 : INT4 interrupt 1 : Timer 3 interrupt
7 Timer 3/INT4 interrupt
source bit
Fig. 2.3.10 Structure of Interrupt edge selection register
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2.3 Serial I/O
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 1 (IREQ1) [Address : 3C16]
B
Name
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T T T
0 INT0 interrupt request bit 1 INT1 interrupt request bit 2 Serial I/O1 receive interrupt
request bit 3 Serial I/O1 transmit interrupt request bit
0 0 0 0 0 0 0 0
4 Timer X interrupt request bit
bit
0 : No interrupt request 1 : Interrupt request Timer 2/INT3 interrupt request 0 : No interrupt request 6 bit 1 : Interrupt request Timer 3/INT4 interrupt request 0 : No interrupt request 7 1 : Interrupt request bit
5 Timer Y interrupt request bit
T "0" is set by software, but not "1.
Fig. 2.3.11 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 2 (IREQ2) [Address : 3D16]
Name B 0 CNTR0 interrupt request bit 1 2 3 4 5 6 7
Function
At reset
RW
T T T T T T T !
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request CNTR1 interrupt request bit 1 : Interrupt request 0 : No interrupt request Serial I/O2 interrupt request bit 1 : Interrupt request 0 : No interrupt request Timer 1/INT2 interrupt 1 : Interrupt request request bit 0 : No interrupt request Timer A interrupt request bit 1 : Interrupt request 0 : No interrupt request Timer B interrupt request bit 1 : Interrupt request 0 : No interrupt request ADT/AD conversion 1 :Interrupt request interrupt request bit Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0."
0 0 0 0 0 0 0 0
T "0" is set by software, but not "1."
Fig. 2.3.12 Structure of Interrupt request register 2
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2.3 Serial I/O
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E16]
B
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 INT0 interrupt enable bit 1 INT1 interrupt enable bit 2 Serial I/O1 receive interrupt
enable bit Serial I/O1 transmit interrupt 3 enable bit
0 0 0 0 0 0 0 0
4 Timer X interrupt enable bit 5 Timer Y interrupt enable bit 6 Timer 2/INT3 interrupt enable
bit Timer 3/INT4 interrupt enable 7 bit
Fig. 2.3.13 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
Name B 0 CNTR0 interrupt enable bit
Function
At reset
RW
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 CNTR1 interrupt enable bit 1 : Interrupt enabled Serial I/O2 interrupt enable bit 0 : Interrupt disabled 2 1 : Interrupt enabled
0 0 0 0 0 0 0 0
3 Timer 1/INT2 interrupt enable
bit 4 Timer A interrupt enable bit
5 Timer B interrupt enable bit 6 ADT/AD conversion interrupt
enable bit 7 Fix this bit to "0."
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
Fig. 2.3.14 Structure of Interrupt control register 2
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2.3 Serial I/O
2.3.3 Serial I/O connection examples (1) Control of peripheral IC equipped with CS pin There are connection examples using a clock synchronous serial I/O mode. Figure 2.3.15 shows connection examples of a peripheral IC equipped with the CS pin.
(1) Only transmission (using the RXD pin as an I/O port) Port SCLK TXD 3807 group CS CLK DATA Peripheral IC (OSD controller etc.)
(2) Transmission and reception
Port SCLK TXD RXD 3807 group
CS CLK IN OUT Peripheral IC (E 2 PROM etc.)
(3) Transmission and reception (Pins RXD and TXD are connected) (Pins IN and OUT in peripheral IC are connected) Port SCLK TXD RXD CS CLK IN OUT
(4) Connecting ICs
Port SCLK TXD RXD Port 3807 group
CS CLK IN OUT Peripheral IC 1
3807 group T1 Peripheral IC T2 2 (E PROM etc.)
T1:
Select an N-channel open-drain output control of TXD pin. 2: Use such OUT pin of peripheral IC as an N-channel opendrain output in high impedance during receiving data.
CS CLK IN OUT Peripheral IC 2
Notes1: "Port" is an output port controlled by software. 2: Use SOUT2 and SIN2 instead of TXD and RXD in the serial I/O2.
Fig. 2.3.15 Serial I/O connection examples (1)
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2.3 Serial I/O
(2) Connection with microcomputer Figure 2.3.16 shows connection examples of the other microcomputers.
(1) Selecting an internal clock
(2) Selecting an external clock
SCLK TXD RXD 3807 group
CLK IN OUT Microcomputer
SCLK TXD RXD 3807 group
CLK IN OUT Microcomputer
(3) Using the SRDY siganl output function (Selecting an external clock)
(4) Using UARTT
SRDY
RDY CLK IN OUT Microcomputer 3807 group Microcomputer TXD RXD RXD TXD
SCLK TXD RXD 3807 group
T : UART can not be used in the serial I/O2. Note : Use SOUT2 and SIN2 instead of TXD and RXD in the serial I/O2.
Fig. 2.3.16 Serial I/O connection examples (2)
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2.3 Serial I/O
2.3.4 Setting of serial I/O transfer data format A clock synchronous or clock asynchronous (UART) is selected as a data format of the serial I/O1. The serial I/O2 operates in a clock synchronous. Figure 2.3.17 shows a setting of serial I/O transfer data format.
1ST-8DATA-1SP
ST LSB MSB SP
1ST-7DATA-1SP
ST LSB MSB SP
1ST-8DATA-1PAR-1SP
ST LSB MSB PAR SP
1ST-7DATA-1PAR-1SP
ST LSB MSB PAR SP
UART
1ST-8DATA-2SP
ST LSB MSB 2SP
1ST-7DATA-2SP
ST LSB MSB 2SP
Serial I/O1
1ST-8DATA-1PAR-2SP
ST LSB MSB PAR 2SP
1ST-7DATA-1PAR-2SP
ST LSB MSB PAR 2SP
Clock synchronous Serial I/O
LSB first
Serial I/O2
Clock synchronous Serial I/O
LSB first (1 to 8 bit optional transfer) MSB first (1 to 8 bit optional transfer)
ST :Start bit SP :Stop bit PAR :Parity bit
Fig. 2.3.17 Setting of Serial I/O transfer data format
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2.3 Serial I/O
2.3.5 Serial I/O application examples (1) Communication using a clock synchronous serial I/O (transmit/receive) Outline : 2-byte data is transmitted and received through the clock synchronous serial I/O. The signal is used for communication control. Figure 2.3.18 shows a connection diagram, and Figure 2.3.19 shows a timing chart.
_____
SRDY1
Transmitting side
Receiving side
P42/INT0
SRDY1
SCLK1 TXD 3807 group
SCLK1 RXD 3807 group
Fig. 2.3.18 Connection diagram [Communication using a clock synchronous serial I/O] Specifications : * * * * The Serial I/O1 is used (clock synchronous serial I/O is selected) Synchronous clock frequency : 125 kHz (f(XIN) = 8 MHz is divided by 64) The SRDY1 (receivable signal) is used. The receiving side outputs the SRDY1 signal at intervals of 2 ms (generated by timer), and 2-byte data is transferred from the transmitting side to the receiving side.
_____ _____
SRDY1
****
SCLK1 TXD
****
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1
****
2 ms
Fig. 2.3.19 Timing chart [Communication using a clock synchronous serial I/O]
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2.3 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 1916)
b7 b0
SIO1STS
Transmit buffer empty flag * Check to be transferred data from the Transmit buffer register to Transmit shift register. * Writable the next transmission data to the Transmit buffer register at being set to "1." Transmit shift register shift completion flag Check a completion of transmitting 1-byte data with this flag "1" : Transmit shift completed
Serial I/O1 control register (Address : 1A16)
b7 b0
SIO1CON
1101
00
BRG counter source selection bit : f(XIN) Serial I/O1 synchronous clock selection bit : BRG/4 Transmit enable bit : Transmit enabled Receive enable bit : Receive disabled Serial I/O1 mode selection bit : Clock synchronous serial I/O Serial I/O1 enable bit : Serial I/O1 enabled
Baud rate generator (Address : 1C16)
b7 b0
BRG
15
Set "division radio - 1"
Interrupt edge selection register (Address : 3A16)
b7 b0
INTEDGE
0
INT0 active edge selection bit : Select INT0 falling edge
Fig. 2.3.20 Setting of related registers at a transmitting side [Communication using a clock synchronous serial I/O]
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2.3 Serial I/O
Receiving side
Serial I/O1 status register (Address : 1916)
b7 b0
SIO1STS
Receive buffer full flag Check a completion of receiving 1-byte data with this flag. "1" : At completing to receive "0" : At reading out a receive buffer Overrun error flag "1" : when data are ready to be transferred to the Receive shift register in the state of storing data into the Receive buffer register.
Serial I/O1 control register (Address : 1A16)
b7 b0
SIO1CON
1111
11
Serial I/O1 synchronous clock selection bit : External clock SRDY1 output enable bit : Use the SRDY1 output Transmit enable bit : Transmit enabled Set this bit to "1," using SRDY1 output. Receive enable bit : Receive enabled Serial I/O1 mode selection bit : Clock synchronous serial I/O Serial I/O1 enable bit : Serial I/O1 enabled
Fig. 2.3.21 Setting of related registers at a receiving side [Communication using a clock synchronous serial I/O]
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2.3 Serial I/O
Control procedure : Figure 2.3.22 shows a control procedure at a transmitting side, and Figure 2.3.23 shows a control procedure at a receiving side.
RESET
qX : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
Initialization 1101XX002 SIO1CON (Address : 1A16) (Address : 1C16) BRG 16--1 INTEDGE (Address : 3A16), bit0 0
.....
IREQ1 (Address:3C16), bit0? 1 IREQ1 (Address : 3C16), bit0 0
0
* Detect INT0 falling edge
TB/RB (Address : 1816)
The first byte of a transmission data
* Write a transmission data The Transmit buffer empty flag is set to "0" by this writing.
SIO1STS (Address : 1916), bit0? 1 TB/RB (Address : 1816) The second byte of a transmission data
0
* Check to be transfered data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag) * Write a transmission data The Transmit buffer empty flag is set to "0" by this writing.
SIO1STS (Address : 1916), bit0? 1
0
* Check to be transfered data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag)
SIO1STS (Address : 1916), bit2? 1
0
* Check a shift completion of the Transmit shift register (Transmit shift register shift completion flag)
Fig. 2.3.22 Control procedure at a transmitting side [Communication using a clock synchronous serial I/O]
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2.3 Serial I/O
RESET
qX : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
Initialization SIO1CON (Address : 1A16)
.....
1111X11X2
Pass 2 ms? Y TB/RB (Address : 1816) Dummy data
N
* An interval of 2 ms is generated by a timer.
* SRDY1 output SRDY1 signal is output by writing data to the TB/RB. Using the SRDY1 , the transmit enabled bit (bit4) of the SIO1CON(address:1A16) is set to "1." 0 * Check a completion of receiving (Receive buffer full flag)
SIO1STS (Address : 1916), bit1? 1 Read out reception data from TB/RB (Address : 1816)
* Receive the first byte data. A Receive buffer full flag is set to "0" by reading data.
SIO1STS (Address : 1916), bit1? 1 Read out reception data from TB/RB (Address : 1816)
0
* Check a completion of receiving (Receive buffer full flag)
* Receive the second byte data. A Receive buffer full flag is set to "0" by reading data.
Fig. 2.3.23 Control procedure at a receiving side [Communication using a clock synchronous serial I/O]
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2.3 Serial I/O
(2) Output of serial data (control of a peripheral IC) Outline : 4-byte data is transmitted and received through the clock synchronous serial I/O. The CS signal is output to a peripheral IC through the port P53.
P53 SCLK1 TXD
CS CLK DATA
CS CLK DATA
P53 SCLK2 SOUT2
CS CLK DATA
CS CLK DATA
3807 group
Peripheral IC
3807 group
Peripheral IC
(1) Example for using Serial I/O1
(2) Example for using Serial I/O2
Fig. 2.3.24 Connection diagram [Output of serial data]
Specifications : * * * * *
The Serial I/O is used. (clock synchronous serial I/O is selected) Synchronous clock frequency : 125 kHz (f(XIN) = 8 MHz is divided by 64) Transfer direction : LSB first The Serial I/O interrupt is not used. ___ The Port P53 is connected to the CS pin ("L" active) of the peripheral IC for a transmission control (the output level of the port P53 is controlled by software).
Figre 2.3.25 shows an output timing chart of serial data.
CS
CLK
DATA
DO0
DO1
DO2
DO3
Note: The SOUT2 pin is in high impedance after completing to transfer data, using the serial I/O2 as an internal clock.
Fig. 2.3.25 Timing chart [Output of serial data]
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2.3 Serial I/O
Figure 2.3.26 shows a setting of serial I/O1 related registers, and Figure 2.3.27 shows a setting of serial I/O1 transmission data.
Serial I/O1 control register (Address : 1A16)
b7 b0
SIO1CON
11011000
BRG count source selection bit : f(XIN) Serial I/O1 synchronous clock selection bit : BRG/4 SRDY1 output enable bit : Not use the SRDY1 signal output function Transmit interrupt source selection bit : Transmit shift operating completion Transmit enable bit : Transmit enabled Receive enable bit : Receive disabled Serial I/O1 mode selection bit : Clock synchronous serial I/O Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B16)
b7 b0
UARTCON
0
P45/TXD P-channel output disable bit : CMOS output
Baud rate generator (Address : 1C16)
b7 b0
BRG
b7
15
Set "division ratio - 1"
Interrupt control register 1 (Address : 3E16)
b0
ICON1
0
Serial I/O1 transmit interrupt enable bit : Interrupt disabled
Interrupt request register 1 (Address : 3C16)
b7 b0
IREQ1
0
Serial I/O1 transmit interrupt request bit Using this bit, check the completion of transmitting 1-byte base data. "1" : Transmit shift completion
Port P5 (Address :0A16)
b7 b0
P5
1
Set to "0" before starting to transmit.
Port P5 direction register (Address :0B16)
b7 b0
P5D
1
P53/INT4 : Output mode
Fig. 2.3.26 Setting of serial I/O1 related registers [Output of serial data] 2-46
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2.3 Serial I/O
Transmit/Receive buffer register (Address : 1816)
b7 b0
TB/RB
Set a transmission data. Check that transmission of the previous data is completed before writing data (bit 3 of the Interrupt request register 1 is set to "1").
Fig. 2.3.27 Setting of serial I/O1 transmission data [Output of serial data]
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2.3 Serial I/O
Control procedure : When the registers are set as shown in Fig. 2.3.26, the Serial I/O1 can transmit 1-byte data simply by writing data to the Transmit buffer register. Thus, after setting the CS signal to "L," write the transmission data to the Receive buffer register on a 1-byte base, and return the CS signal to "H" when the desired number of bytes have been transmitted. Figure 2.3.28 shows a control procedure of serial I/O1.
RESET
qX : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
Initialization SIO1CON (Address : 1A16) 110110002 UARTCON (Address : 1B16), bit4 0 16-1 BRG (Address : 1C16) 0 ICON1 (Address : 3E16), bit3 1 (Address : 0A16), bit3 P5 XXXX1XXX2 P5D (Address : 0B16)
....
q
Set the Serial I/O1. Serial I/O1 transmit interrupt : Disabled Set the CS signal output port. ("H" level output)
q
q
....
N
P5 (Address : 0A16), bit3
0
q
Set the CS signal output level to "L."
IREQ1 (Address : 3C16), bit3
0
q
Set the Serial I/O1 transmit interrupt request bit to "0."
TB/RB (Address : 1816)
a transmission data
q
Write a transmission data. (start to transmit 1-byte data)
IREQ1 (Address : 3C16), bit3? 1
0
q
Check the completion of transmitting 1byte data.
Complete to transmit data? Y
q
q
Use any of RAM area as a counter for counting the number of transmitted bytes. Check that transmission of the target number of bytes has been completed. Return the CS signal output level to "H" when transmission of the target number of bytes is completed.
q
P5 (Address : 0A16), bit3
1
Fig. 2.3.28 Control procedure of serial I/O1 [Output of serial data]
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2.3 Serial I/O
Figure 2.3.29 shows a setting of serial I/O2 related registers, and Figure 2.3.30 shows a setting of serial I/O2 transmission data.
Serial I/O2 control register 1 (Address : 1D16)
b7 b0
SIO2CON1 0 1 0 0 1 0 1 1
Internal synchronous clock selection bits : f(XIN)/64 Serial I/O2 port selection bit : Use the Serial I/O2 SRDY2 output enable bit : Not use the SRDY2 signal output function Transfer direction selection bit : LSB first Serial I/O2 synchronous clock selection bit : Internal clock P71/SOUT2, P72/SCLK2 P-channel output disable bit : CMOS output
Serial I/O2 control register 2 (Address : 1E16)
b7 b0
SIO2CON2
0
111
Optional transfer bits : 8 bit transfer Serial I/O2 I/O comparative signal control bit : Not use SCMP2 output
Interrupt control register 2 (Address : 3F16)
b7 b0
ICON2
0
Serial I/O2 interrupt enable bit : Interrupt disabled
Interrupt request register 2 (Address : 3D16)
b7 b0
IREQ2
0
Serial I/O2 interrupt request bit Using this bit, check the completion of transmitting 1-byte base data. "1" : Transmit completion
Port P5 (Address : 0A16)
b7 b0
P5
1
Set to "0" before starting to transmit.
Port P5 direction register (Address : 0B16)
b7 b0
P5D
1
P53/INT4 : Output mode
Fig. 2.3.29 Setting of serial I/O2 related registers [Output of serial data]
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2.3 Serial I/O
Serial I/O2 register (Address : 1F16)
b7 b0 Set a transmission data. Check that transmission of the previous data is completed before writing data (bit 2 of the Interrupt request register 2 is set to "1").
SIO2
Fig. 2.3.30 Setting of serial I/O2 transmission data [Output of serial data]
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2.3 Serial I/O
Control procedure : When the registers are set as shown in Fig. 2.3.29, the Serial I/O2 can transmit 1-byte data simply by writing data to the Serial I/O2 register. Thus, after setting the CS signal to "L," write the transmission data to the Serial I/O1 register on a 1-byte base, and return the CS signal to "H" when the desired number of bytes have been transmitted. Figure 2.3.31 shows a control procedure of serial I/O2.
RESET
qX : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
Initialization
Fig. 2.3.31 Control procedure of serial I/O2 [Output of serial data]
... .
SIO2CON1 (Address : 1D16) 010010112 SIO2CON2 (Address : 1E16) X0XXX1112 ICON2 (Address : 3F16), bit2 0 P5 (Address : 0A16), bit3 1 P5D (Address : 0B16) XXXX1XXX2
q q q q
Set the Serial I/O2 control register 1. Set the Serial I/O2 control register 2. Serial I/O2 interrupt : Disabled Set the CS signal output port. ("H" level output)
... .
P5 (Address : 0A16), bit3 0
q
Set the CS signal output level to "L."
q
IREQ2 (Address : 3D16), bit2
0
Set the Serial I/O2 interrupt request bit to "0."
SIO2 (Address : 1F16)
a transmission data
q
Write a transmission data. (start to transmit 1-byte data)
IREQ2 (Address : 3D16), bit2? 1
0
q
Check the completion of transmitting 1byte data.
N
q
Complete to transmit data?
q
Y
q
Use any of RAM area as a counter for counting the number of transmitted bytes. Check that transmission of the target number of bytes has been completed. Return the CS signal output level to "H" when transmission of the target number of bytes is completed.
P5 (Address : 0A16), bit3
1
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2.3 Serial I/O
(3) Cyclic transmission or reception of block data (data of a specified number of bytes) between microcomputers [without using an automatic transfer] Outline : When a clock synchronous serial I/O is used for communication, synchronization of the clock and the data between the transmitting and receiving sides may be lost because of noise included in the synchronizing clock. Thus, it is necessary to be corrected constantly. This "heading adjustment" is carried out by using the interval between blocks in this example.
SCLK RXD TXD Master unit
SCLK TXD RXD Slave unit
Note : Use SOUT2 and SIN2 instead of TXD and RXD in the serial I/O2.
Fig. 2.3.32 Connection diagram [Cyclic transmission or reception of block data between microcomputers]
Specifications : * * * * * * * *
The serial I/O1 is used (clock synchronous serial I/O is selected). Synchronous clock frequency : 125 kHz (f(XIN) = 8 MHz is divided by 64) Byte cycle : 488 s Number of bytes for transmission or reception : 8 byte/block Block transfer cycle : 16 ms Block transfer period : 3.5 ms Interval between blocks : 12.5 ms Heading adjustive time : 8 ms
Limitations of the specifications 1. Reading of the reception data and setting of the next transmission data must be completed within the time obtained from "byte cycle - time for transferring 1-byte data" (in this example, the time taken from generating of the Serial I/O1 receive interrupt request to generating of the next synchronizing clock is 428 s). 2. "Heading adjustive time < interval between blocks" must be satisfied.
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2.3 Serial I/O
The communication is performed according to the timing shown below. In the slave unit, when a synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is processed as the beginning (heading) of a block. When a clock is input again after one block (8 byte) is received, the clock is ignored. Figure 2.3.34 shows a setting of related registers.
D0
D1
D2
D7
D0
Byte cycle Block transfer period Block transfer cycle Heading adjustive time
Master side : Read a receive data Write a transmit data Slave side : Read a receive data Write a transmit data
Interval between blocks
Processing for heading adjustment
Fig. 2.3.33 Timing chart [Cyclic transmission or reception of block data between microcomputers]
Master unit
Serial I/O1 control register (Address : 1A16) b7 b0 SIO1CON 1 1 1 1 1 0 0 0 BRG count source : f(XIN) Synchronous clock : BRG/4 Not use the SRDY1 output Transmit interrupt source : Transmit shift operating completion Transmit enabled Receive enabled Clock synchronous serial I/O Serial I/O1 enabled
Slave unit
Serial I/O1 control register (Address : 1A16) b7 b0 SIO1CON 1 1 1 1
01
Not be effected by external clock Synchronous clock : External clock Not use the SRDY1 output Not use the serial I/O1 transmit interrupt Transmit enabled Receive enabled Clock synchronous serial I/O Serial I/O1 enabled
Both of units
UART control register (Address : 1B16) b7 b0 UARTCON
0
P45/TXD pin : CMOS output Baud rate generator (Address : 1C16) b7 b0
BRG
15
Set "division ratio - 1"
Fig. 2.3.34 Setting of related registers [Cyclic transmission or reception of block data between microcomputers]
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2.3 Serial I/O
Control procedure : Control in the master unit After a setting of the related registers is completed as shown in Figure 2.3.34, in the master unit transmission or reception of 1-byte data is started simply by writing transmission data to the Transmit buffer register. To perform the communication in the timing shown in Figure 2.3.33, therefore, take the timing into account and write transmission data. Read out the reception data when the Serial I/O1 transmit interrupt request bit is set to "1," or before the next transmission data is written to the Transmit buffer register. A processing example in the master unit using timer interrupts is shown below.
Interrupt processing routine executed every 488 s Note 1: When using the Index X mode flag (T). Note 2: When using the Decimal mode flag (D). Push the register used in the interrupt processing routine into the stack.
CLT (Note 1) CLD (Note 2) Push register to stack
q
Within a block transfer period? Y Read a reception data
N
q
Generate a certain block interval by using a timer or other functions.
q
Count a block interval counter
Check the block interval counter and determine to start of a block transfer.
Complete to transfer a block? N Write a transmission data
Y
Start a block transfer? Y Write the first transmission data (first byte) in a block
N
Pop registers
q
Pop registers which is pushed to stack.
RTI
Fig. 2.3.35 Control in the master unit
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2.3 Serial I/O
Control in the slave unit After a setting of the related registers is completed as shown in Figure 2.3.34, the slave unit becomes the state which is received a synchronizing clock at all times, and the Serial I/O1 receive interrupt request bit is set to "1" every time an 8-bit synchronous clock is received. By the serial I/O1 receive interrupt processing routine, the data to be transmitted next is written to the Transmit buffer register after received data is read out. However, if no serial I/O1 receive interrupt occurs for more than a certain time (head adjustive time), the following processing will be performed. 1. The first 1 byte data of the transmission data in the block is written into the Transmission buffer register. 2. The data to be received next is processed as the first 1 byte of the received data in the block. Figure 2.3.36 shows the control in the slave unit using a serial I/O1 receive interrupt and any timer interrupt (for head adjustive).
Serial I/O1 receive interrupt processing routine
Timer interrupt processing routine
CLT (Note 1) CLD (Note 2) Push register to stack
q
Push the register used in the interrupt processing routine into the stack. Check the received byte counter to judge if a block has been transfered.
CLT (Note 1) CLD (Note 2) Push register to stack
q
Push the register used in the interrupt processing routine into the stack.
q
Within a block transfer period? Y Read a reception data
N
Heading adjustive counter - 1
Heading adjustive counter = 0? Y
N
A received byte counter +1
Write the first transmission data (first byte) in a block
A received byte counter 8? N
Y
A received byte counter
0
Pop registers Write a transmission data Write any data (FF16) RTI Heading adjustive counter Initialized value (Note 3)
q
Pop registers which is pushed to stack.
Pop registers
q
Pop registers which is pushed to stack.
RTI
Notes 1: When using the Index X mode flag (T). 2: When using the Decimal mode flag (D). 3: In this example, set the value which is equal to the heading adjustive time divided by the timer interrupt cycle as the initialized value of the heading adjustive counter. For example: When the heading adjustive time is 8 ms and the timer interrupt cycle is 1 ms, set 8 as the initialized value.
Fig. 2.3.36 Control in the slave unit
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2.3 Serial I/O
(4) Communication (transmit/receive) using an asynchronous serial I/O (UART) Point : 2-byte data is transmitted and received through an asynchronous serial I/O. The port P42 is used for communication control. Figure 2.3.37 shows a connection diagram, and Figure 2.3.38 shows a timing chart.
Transmitting side
P42
Receiving side
P42
TXD
RXD
3807 group
3807 group
Fig. 2.3.37 Connection diagram [Communication using UART]
Specifications : * The Serial I/O1 is used (UART is selected). * Transfer bit rate : 9600 bps (f(XIN) = 4.9152 MHz is divided by 512) * Communication control using port P42 (The output level of the port P42 is controlled by softoware.) * 2-byte data is transferred from the transmitting side to the receiving side at intervals of 10 ms (generated by timer).
P42
....
TXD
ST D0
D1 D2 D3 D4 D5 D6
D7 SP(2) ST D0 D1 D2 D3
D4 D5 D6 D7 SP(2)
ST D0
....
10 ms
Fig. 2.3.38 Timing chart [Communication using UART]
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2.3 Serial I/O
Table 2.3.1 shows setting examples of Baud rate generator (BRG) values and transfer bit rate values, Figure 2.3.39 shows a setting of related registers at a transmitting side, and Figure 2.3.40 shows a setting of related registers at a receiving side. Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values Transfer bit BRG count at f(XIN) = 4.9152 MHZ at f(XIN) = 7.3728 MHZ at f(XIN) = 8 MHZ rate(bps) source (Note 1) (Note 2) BRG setting value Actual time (bps) BRG setting value Actual time (bps) BRG setting value Actual time (bps) 600 1200 2400 4800 9600 19200 38400 76800 31250 62500 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN) f(XIN) f(XIN) 127(7F16) 63(3F16) 31(1F16) 15(0F16) 7(0716) 3(0316) 1(0116) 3(0316) 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 38400.00 76800.00 191(BF16) 95(5F16) 47(2F16) 23(1716) 11(0B16) 5(0516) 2(0216) 5(0516) 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 38400.00 76800.00 207(CF16) 103(6716) 51(3316) 25(1916) 12(0C16) 5(0516) 2(0216) 5(0516) 15(0F16) 7(0716) 600.96 1201.92 2403.85 4807.69 9615.38 20833.33 41666.67 83333.33 31250.00 62500.00
Notes 1: Equation of transfer bit rate Transfer bit rate (bps) = f(XIN) (BRG setting value + 1) ! 16 ! m
m: when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to "0," a value of m is 1. when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to "1," a value of m is 4. 2: A BRG count source is selected by bit 0 of the Serial I/O1 control register (Address : 1A16).
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2.3 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 1916)
b7 b0
SIO1STS
Transmit buffer empty flag * Check to be transferred data from the Transmit buffer register to the Transmit shift register. * Writable the next transmission data to the Transmit buffer register at being set to "1." Transmit shift register shift completion flag Check a completion of transmitting 1-byte data with this flag. "1" : Transmit shift completed
Serial I/O1 control register (Address : 1A16)
b7 b0
SIO1CON
1001
001
BRG count source selection bit : f(XIN)/4 Serial I/O1 synchronous clock selection bit : BRG/16 SRDY1 output enable bit : Not use SRDY1 output Transmit enable bit : Transmit enabled Receive enable bit : Receive disabled Serial I/O1 mode selection bit : Asynchronous serial I/O(UART) Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B16)
b7 b0
UARTCON
01
00
Character length selection bit : 8 bits Parity enable bit : Parity checking disabled Stop bit length selection bit : 2 stop bits P45/TXD P-channel output disable bit : CMOS output
Baud rate generator (Address : 1C16)
b7 b0
BRG
7
Set
f(XIN) Transfer bit rate ! 16 ! m T
1
T when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to
"0," a value of m is 1.
when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to
"1," a value of m is 4. Port P4 direction register (Address : 0916)
b7 b0
P4D
1
P42/INT0 : Output mode
Port P4 (Address : 0816)
b7 b0
P4
0
P42/INT0 : Set to "1" at starting to communicate.
Fig. 2.3.39 Setting of related registers at a transmitting side [Communication using UART] 2-58
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2.3 Serial I/O
Receiving side
Serial I/O1 status register (Address : 1916)
b7 b0
SIO1STS
Receive buffer full flag Check a completion of receiving 1-byte data with this flag.
"1" : at completing to receive "0" : at reading out a content of the Receive buffer register
Overrun error flag
"1" : when data are ready to be transferred to the Receive shift register in the state of storing data into the Receive buffer register.
Parity error flag
"1" : when parity error occurs at enabled parity.
Framing error flag
"1" : when data can not be received at the timing of setting a stop bit.
Summing error flag
"1" : when even one of the following errors occurs.
* Overrun error * Parity error * Framing error
Serial I/O1 control register (Address : 1A16)
b7 b0
SIO1CON
1010
001
BRG count source selection bit : f(XIN)/4 Serial I/O1 synchronous clock selection bit : BRG/16 SRDY1 output enable bit : Not use SRDY1 out Transmit enable bit : Transmit disabled Receive enable bit : Receive enabled Serial I/O1 mode selection bit : Asynchronous serial I/O(UART) Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B16)
b7 b0
UARTCON
1
00
Character length selection bit : 8 bits Parity enable bit : Parity checking disabled Stop bit length selection bit : 2 stop bits
Baud rate generator (Address : 1C16)
b7 b0
BRG
7
Set
f(XIN) Transfer bit rate ! 16 ! m T
1
T when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to
"0," a value of m is 1.
when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to
"1," a value of m is 4. Port P4 direction register (Address : 0916)
b7 b0
P4D
0
P42/INT0 : Input mode
Fig. 2.3.40 Setting of related registers at a receiving side [Communication using UART]
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2.3 Serial I/O
Control procedure : Figure 2.3.41 shows a control procedure at a transmitting side, and Figure 2.3.42 shows a control procedure at a receiving side.
RESET
L X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
Initialization SIO1CON (Address : 1A16) 1001X0012 UARTCON(Address : 1B16) XXX01X002 BRG (Address : 1C16) 8 --1 P4 (Address : 0816), bit2 0 P4D (Address : 0916) XXXXX1XX2
.... .
* Set port P42 for a communication control.
Pass 10 ms? Y P4 (Address : 0816), bit2 1
N
* An interval of 10 ms is generated by a timer.
* Start of communication. * Write a transmission data The Transmit buffer empty flag is set to "0" by this writing. * Check to be transferred data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag)
TB/RB (Address : 1816)
The first byte of a transmission data
SIO1STS (Address : 1916), bit0? 1 The second byte of a transmission data
0
TB/RB (Address : 1816)
* Write a transmission data The Transmit buffer empty flag is set to "0" by this writing. * Check to be transferred data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag)
0 SIO1STS (Address : 1916), bit0? 1
SIO1STS (Address : 1916), bit2? 1 P4 (Address : 0816), bit2 0
0
* Check a shift completion of the Transmit shift register. (Transmit shift register shift completion flag)
* End of communication
Fig. 2.3.41 Control procedure at a transmitting side [Communication using UART]
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2.3 Serial I/O
RESET
L X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
Initialization SIO1CON (Address : 1A16) UARTCON(Address : 1B16) (Address : 1C16) BRG (Address : 0916) P4D
.....
1010X0012 XXXX1X002 81 XXXXX0XX2
SIO1STS (Address : 1916), bit1? 1 Read out a reception data from RB (Address : 1816)
0
* Check a completion of receiving. (Receive buffer full flag)
* Receive the first 1 byte data A Receive buffer full flag is set to "0" by reading data.
SIO1STS (Address : 1916), bit6? 0
1
* Check an error flag.
SIO1STS (Address : 1916), bit1? 1 Read out a reception data from RB (Address : 1816)
0
* Check a completion of receiving. (Receive buffer full flag)
* Receive the second byte data A Receive buffer full flag is set to "0" by reading data. 1 * Check an error flag. Processing for error
SIO1STS (Address : 1916), bit6? 0
1 P4 (Address : 0816), bit2? 0 SIO1CON (Address : 1A16) SIO1CON (Address : 1A16) 0000X0012 1010X0012 * Countermeasure for a bit slippage
Fig. 2.3.42 Control procedure at a receiving side [Communication using UART]
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2.4 Real time output port
2.4 Real time output port (RTP)
2.4.1 Memory map of real time output port
002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216
Real time port register (RTP) Real time port control register 0 (RTPCON0) Real time port control register 1 (RTPCON1) Real time port control register 2 (RTPCON2) Real time port control register 3 (RTPCON3) Timer A Low-order (TAL) Timer A High-order (TAH) Timer B Low-order (TBL) Timer B High-order (TBH)
Fig. 2.4.1 Memory map of real time output port related registers
2.4.2 Related registers
Real time port register
b7 b6 b5 b4 b3 b2 b1 b0 Real time port register (RTP) [Address : 2A16]
B 0 1 2 3 4 5 6 7
Function
q q
At reset
RW
q
Sets the data to be output to the Real time port. Makes it possible to write data into any of Real time port registers 0 to 7 by specifying the Real time port data pointer (R/W pointer) and writing data into this register. Makes it possible to read any data of Real time port registers 0 to 7 by specifying the Real time port data pointer (R/W pointer) and reading data from this register.
0 0 0 0 0 0 0 0
Fig. 2.4.2 Structure of Real time port register
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2.4 Real time output port
Real time port control register 0
b7 b6 b5 b4 b3 b2 b1 b0 Real time port control register 0 (RTPCON0) [Address : 2B16]
B
Name
Function
At reset
RW
(Note 1) Timer A, Timer B count source 0 : f(XIN)/2 0 selection bit 1 : f(XIN)/16 (Note 2) Real time port * port allocation 0 : 4-4 division (Corresponding ports to the Timer A : selection bit P82-P85 Corresponding ports to the Timer B : P86, P87, P30, P31) 1 1 : 2-6 division (Corresponding ports to the Timer A : P82-P87 Corresponding ports to the Timer B : P30, P31) Timer A start trigger selection bit 0 : Internal trigger (occurs by writing "1" to bit 3.) 1 : External trigger (occurs by inputting trigger to the INT4 pin.) (Note 3) 0 : No operating by writing "0" 1 : Timer A starts counting by writing "1" (when bit 2 is set to "0") 0 : Operating (is set to "0" automatically at generating a start trigger.) 1 : Stop 0 : Internal trigger (occurs by writing "1" to bit 6.) 1 : External trigger (occurs by inputting trigger to the INT4 pin.) (Note 3) 0 : No operating by writing "0" 1 : Timer B starts counting by writing "1" (when bit 5 is set to "0") 0 : Operating (is set to "0" automatically at generating a start trigger.) 1 : Stop
0
0
2
0
Timer A start trigger bit
3
Timer A count source stop bit
0
(Note 4)
4
Timer B start trigger selection bit
1
5
0
Timer B start trigger bit
6
Timer B count source stop bit
0
(Note 4)
7
1
Note 1: In low-speed mode f(XCIN)/2 is selected. 2: In low-speed mode f(XCIN)/16 is selected. 3: The rising edge or falling edge of the external trigger is switched by the INT4 interrupt edge selection bit (bit 4) of the interrupt edge selection register (Address : 3A16.) (However, when the One-shot pulse generation mode is selected, a rising/falling double edge trigger is generated in spite of the contents of the INT4 interrupt edge selection bit.) 4: At a read operation, "0" is always read out.
Fig. 2.4.3 Structure of Real time port control register 0
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2.4 Real time output port
Real time port control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Real time port control register 1 (RTPCON1) [Address : 2C16]
B
Name
b1 b0
Function
At reset
RW
Timer A operating mode 0 selection bits
1 2
3
4 5 6 7
0 0 : 8-repeated load mode 0 1 : 6-repeated load mode 1 0 : 5-repeated load mode 1 1 : One-shot pulse generation mode Real time port data pointer A 0 : R/W pointer switch bit (Note 1) 1 : Output pointer 0 : Interrupts occur when a Real Timer A interrupt mode time port output pointer value selection bit becomes "0002." 1 : Interrupt request occurs in spite of a Real time port output pointer value. Real time port data pointer A b6 b5 b4 0 0 0 : Real time port register 0 0 0 1 : Real time port register 1 0 1 0 : Real time port register 2 0 1 1 : Real time port register 3 1 0 0 : Real time port register 4 1 0 1 : Real time port register 5 1 1 0 : Real time port register 6 (Note 2) 1 1 1 : Real time port register 7 Timer A write pointer 0 : Specify the Timer A0 latch 1 : Specify the Timer A1 latch
0 0 0
0
1 1 1 1
Note 1: Use LDM or STA instruction for specifying the Real time port data pointer A when this bit is switched. When this bit is read, "1" is always read out. 2: When these bits are read, an output pointer is read out.
Fig. 2.4.4 Structure of Real time port control register 1
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2.4 Real time output port
Real time port control register 2
b7 b6 b5 b4 b3 b2 b1 b0 Real time port control register 2 (RTPCON2) [Address : 2D16]
B
Name
b1 b0
Function
At reset
RW
Timer B operating mode 0 selection bits
1 2
3
4 5 6 7
0 0 : 8-repeated load mode 0 1 : 6-repeated load mode 1 0 : 5-repeated load mode 1 1 : One-shot pulse generation mode Real time port data pointer B 0 : R/W pointer switch bit (Note 1) 1 : Output pointer 0 : Interrupts occur when a Real Timer B interrupt mode time port output pointer value selection bit becomes "0002." 1 : Interrupt request occurs in spite of a Real time port output pointer value. Real time port data pointer B b6 b5 b4 0 0 0 : Real time port register 0 0 0 1 : Real time port register 1 0 1 0 : Real time port register 2 0 1 1 : Real time port register 3 1 0 0 : Real time port register 4 1 0 1 : Real time port register 5 1 1 0 : Real time port register 6 (Note 2) 1 1 1 : Real time port register 7 Timer B write pointer 0 : Specify the Timer B0 latch 1 : Specify the Timer B1 latch
0 0 0
0
1 1 1 1
Note 1: Use LDM or STA instruction for specifying the Real time port data pointer B when this bit is switched. When this bit is read, "1" is always read out. 2: When these bits are read, an output pointer is read out.
Fig. 2.4.5 Structure of Real time port control register 2
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2.4 Real time output port
Real time port control register 3
b7 b6 b5 b4 b3 b2 b1 b0 Real time port control register 3 (RTPCON3) [Address : 2E16]
B
Name
Function
At reset
RW
Real time port output selection 0 : I/O port 0 bit (P82) 1 : Real time output port Real time port output selection 1 bit (P83) Real time port output selection 2 bit (P84)
0 0 0 0 0 0 0 0
3 bit (P85) 4 bit (P86) 5 bit (P87) 6 bit (P30) 7 bit (P31)
Real time port output selection Real time port output selection Real time port output selection Real time port output selection Real time port output selection
Fig. 2.4.6 Structure of Real time port control register 3
Timer A Low-order, Timer A High-order, Timer B Low-order, Timer B High-order
b7 b6 b5 b4 b3 b2 b1 b0 Timer A Low-order (TAL), Timer A High-order (TAH) [Address : 2F16 , 3016] Timer B Low-order (TBL), Timer B High-order (TBH) [Address : 3116 , 3216]
B 0 1 2 3 4 5 6 7
Function
q q
At reset
RW
q
Sets the real time output cycle. Writing is performed in the order of low-order and high-order. There are 2 reload latches. When the high-order side is written, the next latch is automatically specified. The latch to be written first can be specified by the Timer A or B write pointer (bit 7 of address 2C16 or 2D16). Reading is performed in the order of high-order and low-order. At a read operation, the value being counted is read out.
1 1 1 1 1 1 1 1
Fig. 2.4.7 Structure of Timer A Low-order, Timer A High-order, Timer B Low-order, Timer B High-order
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2.4 Real time output port
2.4.3 Real time output port application examples Control of stepping motor Outline : The rotation of the stepping motor is controlled by using Real time output ports. Figure 2.4.8 shows a connection diagram.
P82/RTP0 P83/RTP1 P84/RTP2 P85/RTP3 P86/RTP4 P87/RTP5 P30/RTP6 P31/RTP7
Motor 1
Motor 2
3807 group
Fig. 2.4.8 Connection diagram Specifications : * Each of two motors is controlled by using four Real time output ports. * Clock f(XIN) = 8 MHz * The same data table is used for acceleration and deceleration. (20 steps, 500 pps max.) * The value of the Timer A and B are updated by each interrupt processing routine. * When the Timer A and/or B stops, the "L" level is output. Figure 2.4.9 shows the operation patterns of the motor to be controlled in this application example. The Timer A and the Timer B can control the motor independently with different operation patterns.
Pattern 1
Pattern 2
Pattern 3
200 steps at a constant motor speed
Forward rotation 240 20 Reverse rotation 220 260 410 430 450
Step
150 steps at a constant motor speed Speed Fig. 2.4.9 Operation patterns of motor
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The motor is accelerated and decelerated by updating the timer value in the Timer interrupt processing routine. Figure 2.4.10 shows an example of timer table for acceleration and deceleration. A table common to both Timer A and Timer B is used in this application example. As shown in the following figure, the motor speed is controlled by setting a value in the low-order side of the table first at acceleration and by setting a value the high-order side of the table first at deceleration. At a constant motor speed, the motor operation is continued with the last timer value of acceleration.
Setting example for acceleration Timer value set in Timer table (Speed)
Setting of Timer A for changing speed
Setting example for deceleration
Setting of Timer A for changing speed
F42316 A2C216 485616 28B016 1AC116 12F616 0E4116 0B4A16 094116 07CF16 06C216 05F916 056116 04EB16 049B16 045216 042116 040016 03EE16 03E716
( 8pps) ( 12pps) ( 27pps) ( 48pps) ( 73pps) (103pps) (137pps) (173pps) (211pps) (250pps) (289pps) (327pps) (363pps) (397pps) (427pps) (452pps) (473pps) (488pps) (497pps) (500pps)
Timer A Low-order (Address:2F16) TAL
Timer A Low-order (Address:2F16) TAL
2316
Timer A High-order (Address:3016)
E716
Timer A High-order (Address:3016)
TAH
F416 8pps
Timer A Low-order (Address:2F16)
TAH
0316 500pps
Timer A Low-order (Address:2F16)
TAL
C216
Timer A High-order (Address:3016)
TAL
EE16
Timer A High-order (Address:3016)
TAH
A216 12pps
Timer A Low-order (Address:2F16)
TAH
0316 497pps
Timer A Low-order (Address:2F16)
TAL
5616
Timer A High-order (Address:3016)
TAL
0016
Timer A High-order (Address:3016)
TAH
4816 27pps
TAH
0416 488pps
Fig. 2.4.10 Example of timer table for acceleration and deceleration
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2.4 Real time output port
Figure 2.4.11 shows an example of operation pattern table to operate the motor by the operation patterns shown in Figure 2.4.9. The total number of operation patterns, the direction of motor rotation and number of steps at a constant motor speed are set in this table. The motor can be rotated by an arbitrary distance by changing this number of steps. (In this application example, up to 255 steps can be set.) An operation pattern table is set for each of the Timer A and the Timer B.
0416 0016 C816 FF16 9616 0016 6416 FF16 FA16
Total number of operation patterns Forward rotation 200 steps at a constant motor speed Reverse rotation 150 steps at a constant motor speed Forward rotation 100 steps at a constant motor speed Reverse rotation 250 steps at a constant motor speed
Operation pattern 1 Operation pattern 2 Operation pattern 3 Operation pattern 4
Note : "0016" is defined as a forward rotation in this example. "FF16" is defined as a reverse rotation in this example.
Fig. 2.4.11 Example of operation pattern table Figure 2.4.12 shows an example of output data table. Output data is selected in the 4 types of tables shown in Figure 2.4.12 according to the information on forward rotation and reverse rotation referenced in the operation pattern table shown in Figure 2.4.11, and then set in Real time port registers 0 to 7. For example, in case the Timer B continues to control the motor in the forward direction when the data of operation pattern 2 is set after the Timer A has output operation pattern 1, the data of table 3 is set in Real time port registers 0 to 7.
Table 1
Table 2
Table 3
Table 4
RTP7-RTP4 : Forward rotation RTP7-RTP4 : Reverse rotation RTP7-RTP4 : Forward rotation RTP7-RTP4 : Reverse rotation RTP3-RTP0 : Forward rotation RTP3-RTP0 : Forward rotation RTP3-RTP0 : Reverse rotation RTP3-RTP0 : Reverse rotation
b7 Real time port register 7 b0 b7 b0 b7 b0 b7 b0
00 01 00 0 1
b7 b0
10 01 00 0 1
b7 b0
00011001
b7 b0
1 001 1 00 1
b7 b0
Real time port register 6
00 11 00 11
b7 b0
10000011
b7 b0
00111000
b7 b0
10001000
b7 b0
Real time port register 5
00 10 0010
b7 b0
11000 010
b7 b0
00101100
b7 b0
11 00 1 100
b7 b0
Real time port register 4
0110 0110
b7 b0
01000 110
b7 b0
0 1100 10 0
b7 b0
0 100 01 00
b7 b0
Real time port register 3
01000100
b7 b0
0 1100 100
b7 b0
0 1 00 0 11 0
b7 b0
01 10 01 10
b7 b0
Real time port register 2
1 1001 100
b7 b0
00101 100
b7 b0
11 000 01 0
b7 b0
00 10 0 0 10
b7 b0
Real time port register 1
10 0 01 0 0 0
b7 b0
00111000
b7 b0
10 000 01 1
b7 b0
0011 0 0 11
b7 b0
Real time port register 0
10011001
0 0 01 10 0 1
10010001
0 001 0 0 01
Fig. 2.4.12 Example of output data table
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2.4 Real time output port
Figure 2.4.13 shows the waveforms which are output from RTP0 to RTP7 as a result that the Timer A and the Timer B are operated by using the data of Figure 2.4.10 to Figure 2.4.12. This timing chart is for the case where the Timer A controls operation pattern 1 and the Timer B controls operation pattern 3.
Acceleration(20 steps)
A constant motor speed (200 steps)
Deceleration(20 steps)
RTP0 RTP1 RTP2 RTP3
A constant motor speed (100 steps)
Acceleration(20 steps)
Deceleration(20 steps)
RTP4 RTP5 RTP6 RTP7
Fig. 2.4.13 Timing of Real time output
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2.4 Real time output port
Figure 2.4.14 shows the setting method and output timing for the Timer A. The same setting method is used even for the Timer B. Before the count of the Timer A is started, initial values (t1, t2) are set in the Timer A1 latch and the Timer A0 latch. After the count of the Timer A is started, the timer value (t3, ...) is updated in the Timer A interrupt processing routine. The next latch is automatically specified each time a value is set in the timer, so it is not necessary to specify a write latch in bit 7 of RTPCON1 when the timer value is updated. In this application example, the real time output port is switched over to the programmable I/O port after termination of the last output because the "L" level is output from RTP0 to RTP7 when the timer stops as a matter of specification. However, when the count of the Timer A is stopped and the real time output port is switched over to the programmable I/O port after termination of the last output, the next RTP data is output in a short period from an underflow of the Timer A till a count stop of the Timer A. To avoid outputting the next RTP data in the short period, the count of the Timer A is stopped at a start of the last output (though the last output data is output) and the last output period is counted by using different timers (Timer X for the Timer A and timer Y for the Timer B in this case). After that counting, when the Timer X underflows, the real time output port is switched over to the programmable I/O port and the "L" level is output. To continue to output the last output data after the timer stops, just stop the count of the Timer A after termination of the last output. Figure 2.4.14 shows the setting method and output timing and Figure 2.4.15 to Figure 2.4.18 show the control procedures for related registers.
Acceleration (20 steps)
A constant motor speed (200 steps)
Deceleration (20 steps)
RTP0-RTP3
(Note 1)
7
6
4
3
4
3
1
0
(Note 3)
Output pointer value
(Note 2)
7
6
5
3
2
3
2
0
7
Timer A count source stop bit
(Note 4) (Note 4)
Timer A count value
t1
t2
t20 t20
t20 t20
t2
Timer A interrupt request Timer A setting value t3 t4 t20 t20 t20 t20 t19 t18
A B
A : Timer A count Stop, Timer X count Start B : Timer X count Stop, RTP output Port output Use the same setting method for RTP4-RTP7(Timer B). Note 1: 2: 3: Numbers 0 to 7 indicate Real time port registers 0 to 7. The output pointer value (bits 6 to 4 of real time port control register 1) is decreased by 1 at each underflow of the Timer A. Thus, the current output pointer value which is read out indicates the next Real time port register to be output. The "L" level is output after the timer stops. Thus, the last output is executed by creating time by software (Timer X) after the stop of the timer and switching over the real time output port to the programmable I/O port. (For the reason that if the Timer A is stopped during or after an interrupt caused at the termination of the last output, the next data (data of Real time port register 7) is output in a short period from the underflow of the Timer A to the count stop of the Timer A.) To continue to output the last output data after the timer stops, just stop the count of the timer after termination of the last output. Set the timer values t1 and t2 before an RTP output.
4:
Fig. 2.4.14 Setting method and output timing
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2.4 Real time output port
Real time port register (Address : 2A16)
b7 b0
RTP
Sets the data for controlling motor 1. (This data is output at each underflow of the Timer A.) Sets the data for controlling motor 2. (This data is output at each underflow of the Timer B.)
Real time port control register 0 (Address : 2B16)
b7 b0
RTPCON0
10010001
Timer A, Timer B count source selection bit : f(XIN)/16 Real time port*port allocation selection bit : 4-4 division Timer A start trigger selection bit : Internal trigger Timer A start trigger bit : Timer A is started by writing "1" Timer A count source stop bit : Timer A is stopped by writing "1" Timer B start trigger selection bit : Internal trigger Timer B start trigger bit : Timer B is started by writing "1" Timer B count source stop bit : Timer B is stopped by writing "1"
Real time port control register 1 (Address : 2C16)
b7 b0
RTPCON1
11111000
Timer A operating mode selection bits : 8-repeated load mode Real time port data pointer A switch bit "0": For reading the contents of the Real time port register or setting a value in the Real time port register "1": For specifying the output pointer. Timer A interrupt mode selection bit : Causes interrupt request at Timer A underflow Real time port data pointer A : Specify Real time port register 7 Timer A write pointer : Specify the Timer A1 latch
Real time port control register 2 (Address : 2D16)
b7 b0
RTPCON2
11111000
Timer B operating mode selection bits : 8-repeated load mode Real time port data pointer B switch bit "0": For reading the contents of the Real time port register or setting a value in the Real time port register "1": For specifying the output pointer. Timer B interrupt mode selection bit : Causes interrupt request at Timer B underflow Real time port data pointer B : Specify Real time port register 7 Timer B write pointer : Specify the Timer B1 latch
Fig. 2.4.15 Setting of related registers (1)
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2.4 Real time output port
Real time port control register 3 (Address : 2E16)
b7 b0
RTPCON3
Real time port output selection bit (P82/RTP0) Real time port output selection bit (P83/RTP1) Real time port output selection bit (P84/RTP2) Real time port output selection bit (P85/RTP3) Real time port output selection bit (P86/RTP4) Real time port output selection bit (P87/RTP5) Real time port output selection bit (P30/RTP6) Real time port output selection bit (P31/RTP7) "0" : I/O port (At stopping Timer A) "1" : Real time output port (At operating Timer A) "0" : I/O port (At stopping Timer B) "1" : Real time output port (At operating Timer B)
Timer A High-order (Address : 3016)
b7 b0
TAH Timer A Low-order (Address : 2F16)
b7 b0
A value is updated at each underflow of the Timer A. (At acceleration or deceleration)
TAL
Timer B High-order (Address : 3216)
b7 b0
TBH Timer B Low-order (Address : 3116)
b7 b0
A value is updated at each underflow of the Timer B. (At acceleration or deceleration)
TBL
Timer X mode register (Address : 2716)
b7 b0
TXM
01
0000
Timer X operating mode bits : Timer*Event counter mode Timer X write control bit : write to a latch and a timer at the same time Timer X count source selection bits : f(XIN)/16
Timer Y mode register (Address : 2816)
b7 b0
TYM
01
0000
Timer Y operating mode bits : Timer*Event counter mode Timer Y write control bit : write to a latch and a timer at the same time Timer Y count source selection bits : f(XIN)/16
Fig. 2.4.16 Setting of related registers (2)
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2.4 Real time output port
Timer XY control register (Address : 1416)
b7 b0
TXYCON
11
Timer X stop control bit : Stop counting (Set "0" at starting counting) Timer Y stop control bit : Stop counting (Set "0" at starting counting)
Timer X High-order (Address : 2116)
b7 b0
TXH
b7
F416 Timer X Low-order (Address : 2016)
b0
Set a value which need for counting the last output period (62500-1:8pps) of RTP0-RTP3.
TXL
2316
Timer Y High-order (Address : 2316)
b7 b0
TYH
b7
F416 Timer Y Low-order (Address : 2216)
b0
Set a value which need for counting the last output period (62500-1:8pps) of RTP4-RTP7.
TYL
2316
Interrupt control register 1 (Address : 3E16)
b7 b0
ICON1
00
Timer X interrupt enable bit : Interrupt disabled Timer Y interrupt enable bit : Interrupt disabled
Interrupt request register 1 (Address : 3C16)
b7 b0
IREQ1
00
Timer X interrupt request bit (Judge a termination of the last output period of RTP0-RTP3) Timer Y interrupt request bit (Judge a termination of the last output period of RTP4-RTP7)
Fig. 2.4.17 Setting of related registers (3)
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2.4 Real time output port
Interrupt control register 2 (Address : 3F16)
b7 b0
ICON2
11
Timer A interrupt enable bit : Interrupt enabled Timer B interrupt enable bit : Interrupt enabled
Interrupt request register 2 (Address : 3D16)
b7 b0
IREQ2
00
Timer A interrupt request bit Timer B interrupt request bit
Port P3 (Address : 0616)
b7 b0
P3
00
P30/RTP6, P31/RTP7 : Output "L" level at stopping Timer B
Port P3 direction register (Address : 0716)
b7 b0
P3D
11
P30/RTP6, P31/RTP7 : Output mode
Port P8 (Address : 1016)
b7 b0
P8
000000
P82/RTP0-P85/RTP3 : Output "L" level at stopping Timer A P86/RTP4, P87/RTP5 : Output "L" level at stopping Timer B
Port P8 direction register (Address : 1116)
b7 b0
P8D
111111
P82/RTP0-P87/RTP5 : Output mode
Fig. 2.4.18 Setting of related registers (4)
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2.4 Real time output port
Control procedure : Figure 2.4.19-Figure 2.4.22 show control procedures.
RESET Initialization SEI RTPCON0 (Address : 2B16) RTPCON1 (Address : 2C16) RTPCON2 (Address : 2D16) RTPCON3 (Address : 2E16) TXM TYM P3 P3D P8 P8D
.... .... ....
q
X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
9116 F816 F816 0016 01XX00002 01XX00002 XXXXXX002 XXXXXX112 000000XX2 111111XX2
q q
q
q
Timer A and Timer B counts are stopped. Timer A : Selecting "8-repeated load mode", "setting R/W pointer to Real time port register 7", and "specification of Timer A1 latch." Timer B : Selecting "8-repeated load mode", "setting R/W pointer to Real time port register 7", and "specification of Timer B1 latch." P82/RTP0-P87/RTP5, P30/RTP6, P31/RTP7 : I/O port Timer X : Timer*Event counter mode Timer Y : Timer*Event counter mode Initialization for ports ("L" is output at stopping a stepping motor)
(Address : 2716) (Address : 2816) (Address : 0616) (Address : 0716) (Address : 1016) (Address : 1116)
q q
q
q
RTP (Address : 2A16)
Initial value
Each value of the table is set to the Real time port registers 0-7. (A value of R/W pointer is automatically decreased by 1.)
N
A setting of Real time port registers 0-7 is completed ?
Y TAL TAH TAL TAH TBL TBH TBL TBH ICON2 IREQ2 ICON2 IREQ2 (Address : 2F16) (Address : 3016) (Address : 2F16) (Address : 3016) (Address : 3116) (Address : 3216) (Address : 3116) (Address : 3216) (Address : 3F16) , bit4 (Address : 3D16), bit4 (Address : 3F16) , bit5 (Address : 3D16), bit5 Initial value Initial value Initial value Initial value Initial value Initial value Initial value Initial value 1 0 1 0 FC16 FC16 1 1 FF16
q
Set an initial value to the Timer A1 latch. Set an initial value to the Timer A0 latch. Set an initial value to the Timer B1 latch. Set an initial value to the Timer B0 latch.
q
The next latch is specified automatically. The next latch is specified automatically.
q
q
q q q q
Timer A interrupt : Interrupt enabled The Timer A interrupt request bit is set to "0". Timer B interrupt : Interrupt enabled The Timer B interrupt request bit is set to "0". Timer A : An output pointer is set to the Real time port register 7. Timer B : An output pointer is set to the Real time port register 7. Timer A : Start counting Timer B : Start counting The port output is switched to the RTP output.
RTPCON1 (Address : 2C16) RTPCON2 (Address : 2D16) RTPCON0 (Address : 2B16), bit3 RTPCON0 (Address : 2B16), bit6 RTPCON3 (Address : 2E16) A
q q
q
q q
Fig. 2.4.19 Control procedure (1)
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2.4 Real time output port
A Y
All patterns for the Real time port registers 0-3 are completed to output?
N Timer A is stopped completely? N Y Processing for updating data of RTP0-RTP3 output
Y
All patterns for the Real time port registers 4-7 are completed to output?
N Timer B is stopped completely? N Y Processing for updating data of RTP4-RTP7 output
Fig. 2.4.20 Control procedure (2)
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2.4 Real time output port
Processing for updating data of RTP0-RTP3 output
Note : Execute the same processing for RTP4-RTP7 (Timer B.)
q q
RTPCON0 TXL TXH TXYCON
(Address : 2B16), bit4 (Address : 2016) (Address : 2116) (Address : 1416), bit0
1 2316 F416 0
Timer A count is stopped. Set the last output period Timer X count is started.
q
IREQ1 (Address : 3C16), bit4 1 1 TXYCON (Address : 1416), bit0 (A) RTPCON3 (Address : 2E16) (A) (A)&F016 (A) RTPCON3 (Address : 2E16) *Store the last output data to RAM (A) RTPCON1 (Address : 2C16) CLC (A) (A)+1016 (A) (A)&7816 (A) RTPCON1 (Address : 2C16) RTP (Address : 2A16) (A) (A)&F016 (A) The last data (A)
0
q
Is the last output completed?
q q
Timer X count is stopped. RTP0-RTP3 output is switched to a port output.
q
A RTP data pointer value is set back the previous value ( the last output pointer.)
q
Read out the last output data. 4 low-order bits of the last output data are stored to RAM.
q
All patterns are completed? Y
N
q
Data for the Real time port register is updated.
RTPCON1(Address : 2C16) TAL TAH TAL TAH TBL TBH TBL TBH
Output pointer Initial value Initial value Initial value Initial value Initial value Initial value Initial value Initial value 0
q
Judges whether real time port registers 0 to 3 output the data for forward rotation or the data for reverse rotation next in order to determine which output data table is to be used. Sets the output pointer so that the output may be started with the last output data of the previous pattern. Set an initial value to the Timer A1 latch. Set an initial value to the Timer A0 latch. Set an initial value to the Timer B1 latch. Set an initial value to the Timer B0 latch The next latch is specified automatically. The next latch is specified automatically.
IREQ2 (Address : 3D16), bit4
RTPCON0(Address : 2B16), bit3 1 (A) RTPCON3 (Address : 2E16) (A) (A) or 0F16 RTPCON3(Address : 2E16) (A)
Fig. 2.4.21 Control procedure (3)
.... .... ....
(Address : 2F16) (Address : 3016) (Address : 2F16) (Address : 3016) (Address : 3116) (Address : 3216) (Address : 3116) (Address : 3216)
q
q
q
q
q
Set the Timer A interrupt request bit to "0." Timer A : Start counting The port output is switched to the RTP output.
q q
Set the all patterns completion flag RTS
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2.4 Real time output port
Timer A interrupt processing routine (Note)
Note : Execute the same processing for Timer B.
During a constant motor speed?
N
Y (A constant motor speed processing)
Counter + 1 During accelerating?
N Y
(An acceleration processing)
All number of constant motor speed steps are completed to output?
Counter + 1
N
Y
All number of acceleration steps are completed to output?
N
Set the deceleration flag
(A deceleration processing is executed next time)
(A deceleration processing)
Y Y
A number of steps (number of deceleration steps - 1) is completed to output?
Set the constant motor speed flag
(A constant motor speed processing is executed next time)
Counter
0016
(Stop completely)
N
Counter
0016
Counter + 1
Set the completion stop flag Counter 0016 Set a value of a timer table for deceleration in order low-order to high-order of Timer A.
RTI
Fig. 2.4.22 Control procedure (4)
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2.5 A-D converter
2.5 A-D converter
2.5.1 Memory map of A-D conversion
003416 003516 003D16 003F16
A-D control register (ADCON) A-D conversion register (AD) Interrupt request register 2 (IREQ2) Interrupt control register 2 (ICON2)
Fig. 2.5.1 Memory map of A-D conversion related registers
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2.5 A-D converter
2.5.2 Related registers
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (ADCON) [Address : 3416]
B
Name
b3 b2 b1 b0
Function
0 0 0 1 : P74/AN1 0 0 1 0 : P75/AN2 0 0 1 1 : P76/AN3 0 1 0 0 : P77/AN4 0 1 0 1 : P60/AN5 0 1 1 0 : P61/AN6 0 1 1 1 : P62/AN7 1 0 0 0 : P63/CMPIN/AN8 1 0 0 1 : P64/CMPREF/AN9 1 0 1 0 : P65/DAVREF/AN10 1 0 1 1 : P80/DA3/AN11 1 1 0 0 : P81/DA4/AN12 When A-D trigger is invalid 0 : Start conversion by writing to "0" 1 : Conversion completed When A-D trigger is valid 0 : Conversion in progress 1 : Conversion completed 0 : Connect only at A-D conversion 1 : Connect all time 0 : A-D external tirgger invalid 1 : A-D external tirgger valid 0 : At conversion completed 1 : At ADT falling input
At reset
RW
0 Analog input pin selection bits 0 0 0 0 : P73/SRDY2/ADT/AN0 1
0
0
2
0
3 4 AD conversion completion bit
0
1
5 ADVREF input switch bit 6 AD external trigger valid bit 7 Interrupt source selection bit
0 0 0
Fig. 2.5.2 Structure of A-D control register
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion register (AD) [Address : 3516]
B Function 0 The read-only register which A-D conversion results are stored. 1 2 3 4 5 6 7
At reset
RW
! ! ! ! ! ! ! !
? ? ? ? ? ? ? ?
Fig. 2.5.3 Structure of A-D conversion register
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2.5 A-D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 2 (IREQ2) [Address : 3D16]
B Name CNTR0 interrupt request bit 0 1 CNTR1 interrupt request bit
Function
0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T T !
0 0 0 0 0 0 0 0
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 2 Serial I/O2 interrupt request bit 1 : Interrupt request 3 Timer 1/INT2 interrupt request 0 : No interrupt request bit 1 : Interrupt request 0 : No interrupt request 4 Timer A interrupt request bit 1 : Interrupt request
5 Timer B interrupt request bit
0 : No interrupt request 1 : Interrupt request 6 ADT/AD conversion interrupt 0 : No interrupt request request bit 1 : Interrupt request 7 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0." T "0" is set by software, but not "1."
Fig. 2.5.4 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
Name B 0 CNTR0 interrupt enable bit 1 CNTR1 interrupt enable bit 2 Serial I/O2 interrupt enable
bit
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 0 0 0 0 0 0 0
3 Timer 1/INT2 interrupt enable
bit 4 Timer A interrupt enable bit
5 Timer B interrupt enable bit 6 ADT/AD conversion interrupt
enable bit
7 Fix this bit to "0."
Fig. 2.5.5 Structure of Interrupt control register 2
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2.5 A-D converter
2.5.3 A-D conversion application example Conversion of Analog input voltage Outline : The analog input voltage input from the sensor is converted into digital values. Refer to the following examples for using an internal trigger or an external trigger. (1) Read for analog signal using an internal trigger Figure 2.5.6 shows a connection diagram, and Figure 2.5.7 shows a setting of related registers.
ADVREF P74/AN1 AVSS VSS 3807 group
Reference voltage Sensor
Fig. 2.5.6 Connection diagram [Read for analog signal using an internal trigger] Specifications : * The analog input voltage input from the sensor is converted into digital values. (Note) * The P74/AN1 pin is used as an analog input pin. * A-D conversion start with an internal trigger (by setting bit 4 of A-D control register to "0" ). Note : Example When a reference voltage, 5.12 V is input to the ADVREF pin and a voltage, 4 V to the P74/AN1 pin, an input voltage is converted to a following value. (256 / 5.12 V) ! 4 V = 200 (C816)
A-D control register (Address : 3416) ADCON 0 10001
Analog input pin selection bits : Select the P74/AN1 pin AD conversion completion bit : Conversion completed (set to "0" at starting) AD external trigger valid bit : Invalid (internal trigger)
A-D conversion register (Address : 3516) AD
(read-only) Store a result of A-D conversion (Note) Note: Read out a result of A-D conversion after bit 4 of the A-D control register (ADCON) is set to "1."
Port P7 direction register (Address : 0F16) P7D 0
P74/AN1 pin : Input mode
Fig. 2.5.7 Setting of related registers [Read for analog signal using an internal trigger]
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2.5 A-D converter
Control procedure : By setting the related registers as shown in Figure 2.5.8, the analog input voltage input from the sensor are converted into digital values.
qX : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
* Select the P74/AN1 pin as an analog input pin.
ADCON (Address : 3416) X0X100012 P7D (Address : 0F16) XXX0XXXX2 ADCON (Address : 3416), bit4 0
External trigger is invalid.
* P74/AN1 pin:Input mode * Start A-D conversion.
ADCON (Address : 3416), bit4? 1 Read out AD (Address : 3516)
0
* Check the completion of A-D conversion.
* Read out the conversion result.
Fig. 2.5.8 Control procedure [Read for analog signal using an internal trigger]
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2.5 A-D converter
(2) Read for analog signal using an external trigger Figure 2.5.9 shows a connection diagram, and Figure 2.5.10 shows a setting of related registers.
ADVREF P74/AN1
P73/SRDY2/ADT/AN0
Reference voltage Sensor External trigger
AVSS VSS 3807 group
Fig. 2.5.9 Connection diagram [Read for analog signal using an external trigger] Specifications : * The analog input voltage input from the sensor is converted into digital values. (Note) * The P74/AN1 pin is used as an analog input pin. * A-D _____ conversion start with an external trigger (by inputting a falling edge to the P73/SRDY2/ADT/AN0 pin ). Note : Example When a reference voltage, 5.12 V is input to the ADVREF pin and a voltage, 4 V to the P74/AN1 pin, an input voltage is converted to a following value. (256 / 5.12 V) ! 4 V = 200 (C816)
A-D control register (Address : 3416) ADCON 1 10001
Analog input pin selection bits : Select the P74/AN1 pin AD conversion completion bit : Conversion completed (Note 1) AD external trigger valid bit :Valid
A-D conversion register (Address : 3516) AD
(read-only) Store a result of A-D conversion (Note 2)
Port P7 direction register (Address : 0F16) P7D 00
P73/SRDY2/ADT/AN0 pin : Input mode P74/AN1 pin : Input mode Note 1: An external trigger becomes valid by setting this bit to "1." When bit 6 is set to "1" and bit 4 to "0" at the same time, A-D comversion may start at that time. 2: Read out a result of A-D conversion after bit 4 of the A-D control register (ADCON) is set to "1."
Fig. 2.5.10 Setting of related registers [Read for analog signal using an external trigger]
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2.5 A-D converter
Control procedure : By setting the related registers as shown in Figure 2.5.11, the analog input voltage input from the sensor are converted into digital values.
~ ~
ADCON (Address : 3416) P7D (Address : 0F16) X1X100012 XXX00XXX2
qX : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
* Select the P74/AN1 pin as an analog input pin.
External trigger is valid.
* P73/SRDY2/ADT/AN0 pin : Input mode
ADCON (Address : 3416), bit4? 0
1
* Check the start of A-D conversion.
ADCON (Address : 3416), bit4? 1 Read out AD (Address : 3516)
0
* Check the completion of A-D conversion.
* Read out the conversion result.
~ ~
Fig. 2.5.11 Control procedure [Read for analog signal using an external trigger]
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2.6 Reset
2.6 Reset
2.6.1 Connection example of reset IC
1
VCC
Power source
M62022L
GND
3
5
Output
RESET
Delay capacity
4
0.1
F VSS
3807 group
Fig. 2.6.1 Example of Poweron reset circuit
Figure 2.6.2 shows the system example which switch to the RAM backup mode by detecting a drop of the system power source voltage with the INT interrupt.
System power source voltage +5
+ 7
VCC
VCC1 RESET
2
5
RESET
VCC2
INT
3
INT VSS
1
V1 GND Cd
4
6
3807 group
M62009L, M62009P, M62009FP
Fig. 2.6.2 RAM back-up system
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APPLICATION
2.7 Application circuit example
2.7 Application circuit example
Refer to the following applicaion circuit examples using the 3807 group microcomputer. * Hot water supply system application example ........................................................... Figure 2.7.1 * CD changer (car audio) application example ............................................................. Figure 2.7.2 * Hot water washing toilet seat applicaiton example ................................................... Figure 2.7.3
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3807 GROUP USER'S MANUAL
Hot water supply system application example
3807 group
3
P00-P02 P10 P03 P04 AN0 AN6 RTP0 RTP1 P11
E2PROM
Igniter
Electromagnetic valve 1 Electromagnetic valve 2
Flame sensor
Mode setting
Timer A (16-bit)
AN1 (Real time port output) AN2 (Real time port output) AN3
(Pulse period measurement mode)
Water level sensor
Timer B (16-bit) Timer X (16-bit) Timer Y (16-bit)
(Event counter mode) CNTR1 CNTR0
Hot water supply comparison valve Fan motor
Water temperature thermistor
Fig. 2.7.1 Hot water supply system application example
AN4
Hot water supply thermistor
Hot water pour thermistor
Timer 1 (8-bit)
RXD TXD
3807 GROUP USER'S MANUAL
Flux sensor
Timer 2 (8-bit)
AN5
Driver
Remote-controller 1 Remote-controller 2
VR WDT
XIN
Timer 3 (8-bit)
P20 RESET XOUT
WDT
Reset IC
For controlling
APPLICATION
8MHZ
2.7 Application circuit example
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2-90
Car audio CD changer application example
3807 group System controller microcomputer
****
APPLICATION
2.7 Application circuit example
Eject/CD SELECT1-6
PORT CD changer mechanism unit SI/O1 PORT INT1
Fig. 2.7.2 CD changer (car audio) application example
3807 GROUP USER'S MANUAL
LAM controller for cars
Eject PORT AD AD
Power source monitor
Sensor from CD changer mechanism unit
SI/O2 INT2 F_OK
Clock for low-speed mode
CD*DSP
Clock for middle-/high-speed mode
Warm water washing toilet seat application example
3807 group
INT0
Timer 2 (8-bit) phase control Timer 3 (8-bit) Timer 1 (8-bit)
Commercial power source input Hot air heater output Toilet seat heater output
Warm water heater output
Nozzle position detection AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8
Pulse output mode Timer Y (16-bit) Pulse period measurement mode resolution = 250 ns WDTL (8-bit) Timer X (16-bit) 8 repeated load mode resolution = 250 ns Timer B (16-bit) 8 repeated load mode resolution = 250 ns Timer A (16-bit)
Water temperature detection 1
Water temperature detection 2 RTP 4
Water temperature detection 3
Water temperature detection 4 RTP 4
Stepping motor control 1 Stepping motor control 2 Buzzer output Electromagnetic valve control output LED output Hot air fan output
Toilet seat temperature detection
Room temperature detection
Power source voltage detection
Fig. 2.7.3 Hot water washing toilet seat applicaiton example
3807 GROUP USER'S MANUAL
Warm water flux detection CNTR1
Remote-controller
SW input 10
XIN
TxD
WDTH (8-bit) Runaway detection
XOUT
Deodorization contorl output Pump output 8MHZ
APPLICATION
2.7 Application circuit example
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CHAPTER 3 APPENDIX
3.1 Electrical characteristics 3.2 Standard characteristics 3.3 Notes on use 3.4 Countermeasures against noise 3.5 List of registers 3.6 Mask ROM ordering method 3.7 Mark specification form 3.8 Package outline 3.9 Machine instructions 3.10 List of instruction codes 3.11 SFR memory map 3.12 Pin configuration
APPENDIX
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings Table 3.1.1 Absolute maximum ratings
Symbol VCC CMPVCC VI Power source voltage Analog comparator power source voltage Input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P65, P70-P77, P80-P87, ADVREF
____________
Parameter
Conditions
Ratings -0.3 to 7.0 -0.3 to 7.0 -0.3 to VCC +0.3
Unit V V V
VI VI VI VI VID VO
Input voltage Input voltage Input voltage In-phase input voltage
RESET, XIN CNVSS (ROM version) CNVSS (PROM version) CMPIN, CMPREF |CMPIN-CMPREF| P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P62, P65, P70-P77, P80-P87, XOUT CMPOUT
All voltages are based on VSS. Output transistors are cut off.
-0.3 to VCC +0.3 -0.3 to 7 -0.3 to 13 -0.3 to CMPVCC +0.3 CMPVCC -0.3 to VCC +0.3
V V V V V V
Differential input voltage Output voltage
VO Pd Topr Tstg
Output voltage Power dissipation
-0.3 to CMPVCC +0.3 Ta = 25C 500 -20 to 85 -40 to 125
V mW C C
Operating temperature Storage temperature
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3807 GROUP USER'S MANUAL
APPENDIX
3.1 Electrical characteristics
3.1.2 Recommended operating conditions Table 3.1.2 Recommended operating conditions (1) (Vcc = 2.7 to 5.5 V, Ta = - 20 to 85 C, unless otherwise noted)
Symbol VCC VSS ADVREF DAVREF CMPVCC AVSS VIA VIH Power source voltage Power source voltage A-D comparator reference voltage D-A comparator reference voltage Analog comparator power source voltage Analog power source voltage A-D comparator input voltage "H" input voltage AN0--AN12 P00--P07, P10--P17, P30, P31, P33--P37, P40--P47, P50--P57, P60--P65, P70--P77, P80--P87 P20--P27, P32 (Note)
______
Parameter f(XIN) 4.1MHz
Limits Min. 2.7 4.0 2.0 2.7 VCC 0 AVSS 0.8VCC VCC VCC f(XIN) = 8MHz Typ. 5.0 5.0 0 VCC VCC Max. 5.5 5.5
Unit V V V V V V V V V
VIH VIH VIH VIL
"H" input voltage (CMOS input level selected) P20--P27, P32 "H" input voltage (TTL input level selected) "H" input voltage "L" input voltage RESET, XIN, CNVSS P00--P07, P10--P17, P30, P31, P33--P37, P40--P47, P50--P57, P60--P65, P70--P77, P80--P87 P20--P27, P32 (Note)
______
0.8VCC 2.0 0.8VCC 0
VCC VCC VCC 0.2VCC
V V V V
VIL VIL VIL VIL
"L" input voltage (CMOS input level selected) P20--P27, P32 "L" input voltage (TTL input level selected) "L" input voltage "L" input voltage RESET, CNVSS XIN
0 0 0 0
0.2VCC 0.8 0.2VCC 0.16VCC
V V V V
Note: When Vcc is 4.0 to 5.5 V.
Table 3.1.3 Recommended operating conditions (2) (Vcc = 2.7 to 5.5 V, Ta = - 20 to 85 C, unless otherwise noted)
Symbol IOH(peak) IOH(peak) IOL(peak) IOL(peak) Parameter "H" total peak output current (Note) "H" total peak output current (Note) "L" total peak output current (Note) "L" total peak output current (Note) P24-P27 "L" total peak output current (Note) "H" total average output current (Note) "H" total average output current (Note) "L" total average output current (Note) "L" total average output current (Note) P24-P27 "L" total average output current (Note) P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77 P00-P07, P10-P17, P20-P23, P30-P37, P80-P87 in single chip mode in memory expansion mode and microprocessor mode P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77 P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77 P00-P07, P10-P17, P20-P23, P30-P37, P80-P87 in single chip mode in memory expansion mode and microprocessor mode P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77 Limits Min. Typ. Max. -80 -80 80 80 80 80 -40 -40 40 40 40 40 Unit mA mA mA mA mA mA mA mA mA mA mA mA
IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg)
IOL(avg)
Note: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100ms. The total peak current is the peak value of all the currents.
3807 GROUP USER'S MANUAL
3-3
APPENDIX
3.1 Electrical characteristics
Table 3.1.4 Recommended operating conditions (3) (Vcc = 2.7 to 5.5 V, Ta = - 20 to 85 C, unless otherwise noted)
Symbol IOH(peak) "H" peak output current (Note 1) Parameter P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77, P80-P87 P00-P07, P10-P17, P20-P23, P30-P37, P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77, P80-P87 in single chip mode in memory expansion mode and microprocessor mode P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77, P80-P87 P00-P07, P10-P17, P20-P23, P30-P37, P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77, P80-P87 in single chip mode in memory expansion mode and microprocessor mode High-speed mode 4.0V VCC 5.5V High-speed mode 2.7V VCC 4.0V Middle-speed mode 4.0V VCC 5.5V Middle-speed mode (Note 5) 2.7V VCC 4.0V Middle-speed mode (Note 5) 2.7V VCC 4.0V f(XCIN) Note1: 2: 3: 4: Sub-clock input oscillation frequency (Note 3, 4) 32.768 Limits Min. Typ. Max. -10 Unit mA
IOL(peak)
"L" peak output current (Note 1)
10
mA
IOL(peak)
"L" peak output current (Note 1) P24-P27 "H" average output current (Note 2)
20 10 -5
mA mA mA
IOH(avg)
IOL(avg)
"L" average output current (Note 2)
5
mA
IOL(avg)
"L" average output current (Note 2) P24-P27 Main clock input oscillation frequency (Note 3)
15 5 8 3VCC-4 8 8 3VCC-4 50
mA mA MHz MHz MHz MHz MHz kHz
f(XIN)
The peak output current is the peak current flowing in each port. The average output current IOL (avg), IOH (avg) in an average value measured over 100ms. When the oscillation frequency has a duty cyde of 50%. When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) f(XIN)/ 3. 5: When using the timer X/Y, timer A/B (real time output port), timer 1/2/3, serial I/O1, serial I/O2, and A-D converter, set the main clock input oscillation frequency to the max. 3 Vcc-4 (MHz).
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3807 GROUP USER'S MANUAL
APPENDIX
3.1 Electrical characteristics
3.1.3 Electrical characteristics Table 3.1.5 Electrical characteristics (1) (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted)
Symbol VOH Parameter "H" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P62, P65, P70-P77, P80-P87, CMPOUT (Note 1) "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P62, P65, P70-P77, P80-P87, CMPOUT Hysteresis Hysteresis Hysteresis "H" input current P42, P43, P51-P55, P73 (Note 2), CNTR0, CNTR1, INT0-INT4, ADT RXD, SCLK1, SIN2, SCLK2
____________
Test conditions IOH = -10mA VCC = 4.0 to 5.5V IOH = -1.0mA VCC = 2.7 to 5.5V IOL = 10mA VCC = 4.0 to 5.5V IOL = 1.6mA VCC = 2.7 to 5.5V
Limits Min. VCC-2.0 VCC-1.0 2.0 0.4 0.4 0.5 0.5 Typ. Max.
Unit V V V V V V V
VOL
VT+-VT- VT+-VT- VT+-VT- IIH
RESET P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P65, P70-P77, P80-P87
____________
VI = VCC (Pin floating. Pull-up transistors "off") VI = VCC VI = VCC VI = VSS (Pin floating. Pull-up transistors "off") VI = VSS VI = VSS Pull-up transistors "on" VI = VSS When clock stopped 2.0 -4 -0.2 4
5.0
A
IIH IIH IIL
"H" input current "H" input current "L" input current
RESET, CNVSS XIN P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P65, P70-P77, P80-P87
____________
5.0 -5.0
A A A
IIL IIL IIL VRAM
"L" input current "L" input current "L" input current RAM hold voltage
RESET, CNVSS XIN P00-P07, P10-P17, P20-P27
-5.0
A A mA
5.5
V
Note1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". P71, and P12 are measured when the P71/SOUT2 and P72/SCLK2 P-channel output disable bit of the serial I/O2 control register 1 (bit 7 of address 001D16). 2: P73 is measured when the AD external trigger valid bit of the A-D control register (bit 6 of address 003416) is "1".
3807 GROUP USER'S MANUAL
3-5
APPENDIX
3.1 Electrical characteristics
Table 3.1.6 Electrical characteristics (2) (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted)
Symbol ICC Parameter Power source current Test conditions High-speed mode f(XIN) = 8MHz f(XCIN) = 32.768kHz Output transistors "off" High-speed mode f(XIN) = 8MHz (in WIT state) f(XCIN) = 32.768kHz Output transistors "off" Low-speed mode f(XIN) = stopped f(XCIN) = 32.768kHz Low-power dissipation mode (CM3 = 0) Output transistors "off" Low-speed mode f(XIN) = stopped f(XCIN) = 32.768kHz (in WIT state) Low-power dissipation mode (CM3 = 0) Output transistors "off" Low-speed mode (VCC = 3V) f(XIN) = stopped f(XCIN) = 32.768kHz Low-power dissipation mode (CM3 = 0) Output transistors "off" Low-speed mode (VCC = 3V) f(XIN) = stopped f(XCIN) = 32.768kHz (in WIT state) Low-power dissipation mode (CM3 = 0) Output transistors "off" Middle-speed mode f(XIN) = 8MHz f(XCIN) = stopped Output transistors "off" Middle-speed mode f(XIN) = 8MHz (in WIT state) f(XCIN) = stopped Output transistors "off" Increment when A-D conversion is executed f(XIN) = 8MHz All oscillation stopped (in STP state) Output transistors "off" CMPICC Analog comparator Power source current Ta = 25C Ta = 85C 200 Limits Min. Typ. 6.8 Max. 13 Unit mA
1.6
mA
60
200
A
20
40
A
20
55
A
5.0
10.0
A
4.0
7.0
mA
1.5
mA
800 0.1 1.0 10 500
A A A A
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3807 GROUP USER'S MANUAL
APPENDIX
3.1 Electrical characteristics
3.1.4 A-D converter characteristics Table 3.1.7 A-D converter characteristics (Vcc = 2.7 to 5.5 V, Vss = AVss = 0 V, ADVREF = 2.0 V to Vcc, Ta = - 20 to 85 C, unless otherwise noted)
Symbol -- -- tCONV RLADDER IADVREF II(AD) Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current A-D port input current ADVREF ADVREF
"on" "off"
Parameter
Test conditions
Limits Min. Typ. Max. 8 2 50 12 35 150 100 200 5 5.0
Unit Bits LSB tc() k A A A
VCC = ADVREF = 5.0V
ADVREF = 5.0V
50
3.1.5 D-A converter characteristics Table 3.1.8 D-A converter characteristics (Vcc = 2.7 to 5.5 V, Vss = AVss = 0 V, DAVREF = 2.7 V to Vcc, Ta = - 20 to 85 C, unless otherwise noted)
Symbol -- -- tsu Ro IDAVREF Resolution Absolute accuracy Setting time Output resistor Reference power source input current (Note) 1 2.5 VCC = 4.0 to 5.5V VCC = 2.7 to 4.0V Parameter Test conditions Min. Limits Typ. Max. 8 1.0 2.5 3 4 3.2 Unit Bits % % s k mA
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being "0016".
3.1.6 Analog comparator characteristics Table 3.1.9 Analog comparator characteristics (Vcc = 2.7 to 5.5 V, Vss = AVss = 0 V, CMPVcc = 2.7 V to Vcc, Ta = - 20 to 85 C, unless otherwise noted)
Symbol VIO IB IIO VICM AV tPD Input offset voltage Input bias current Input offset current In-phase input voltage range Voltage gain Response time CMPVCC = 5.0V CMPREF = 2.5V 1.2 60 2500 ns Parameter Test conditions CMPVCC = 5.0V CMPREF = 2.5V, Rs = 0 Limits Min. Typ. 3 Max. 50 5 5 CMPVCC -0.5 Unit mV A A V
3807 GROUP USER'S MANUAL
3-7
APPENDIX
3.1 Electrical characteristics
3.1.7 Timing requirements Table 3.1.10 Timing requirements (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted)
Symbol
____________
Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT4 input "H" pulse width INT0 to INT4 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 clock input set up time Serial I/O1 clock input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 clock input set up time
Limits Min. 2 125 50 50 200 80 80 80 80 800 370 370 220 100 1000 400 400 200 200 Typ. Max.
Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RXD-SCLK1) th(SCLK1-RXD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2)
th(SCLK2-SIN2) Serial I/O2 clock input hold time Note: When bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16 is "0" (UART).
Table 3.1.11 Timing requirements (2) (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted)
Symbol
____________
Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT4 input "H" pulse width INT0 to INT4 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 clock input set up time Serial I/O1 clock input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 clock input set up time
Limits Min. 2 243 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max.
Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RXD-SCLK1) th(SCLK1-RXD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2)
th(SCLK2-SIN2) Serial I/O2 clock input hold time Note: When bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16 is "0" (UART).
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3807 GROUP USER'S MANUAL
APPENDIX
3.1 Electrical characteristics
3.1.8 Switching characteristics Table 3.1.12 Switching characteristics (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted)
Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TXD) tv(SCLK1-TXD) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2-SOUT2) tv(SCLK2-SOUT2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Fig. 3.1.1 10 10 0 30 30 30 Fig. 3.1.1 tC(SCLK2)/2-160 tC(SCLK2)/2-160 200 -30 30 30 Test conditions Fig. 3.1.1 Limits Min. tC(SCLK1)/2-30 tC(SCLK1)/2-30 140 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: When the P71/SOUT2, P72/SCLK2 P-channel output disable bit of the serial I/O2 control register1 (bit 7 of address 001D16) is "0". 3: XOUT pin is excluded.
Table 3.1.13 Switching characteristics (2) (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted)
Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TXD) tv(SCLK1-TXD) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2-SOUT2) tv(SCLK2-SOUT2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Fig. 3.1.1 20 20 0 50 50 50 Fig. 3.1.1 tC(SCLK2)/2-240 tC(SCLK2)/2-240 400 -30 50 50 Test conditions Fig. 3.1.1 Limits Min. tC(SCLK1)/2-50 tC(SCLK1)/2-50 350 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: When the P71/SOUT2, P72/SCLK2 P-channel output disable bit of the serial I/O2 control register1 (bit 7 of address 001D16) is "0". 3: XOUT pin is excluded.
3807 GROUP USER'S MANUAL
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APPENDIX
3.1 Electrical characteristics
3.1.9 Timing requirements in memory expansion mode and microprocessor mode Table 3.1.14 Timing requirements in memory expansion and microprocessor mode (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, in high-speed mode, unless otherwise noted)
Symbol
____ _________
Parameter ONW input set up time
_________
Limits Min. -20 -20 50 0 -20 -20 50 0 Typ. Max.
Unit ns ns ns ns ns ns ns ns
tsu(ONW-) th(-ONW) tsu(DB-) th(-DB) tsu(ONW-RD), tsu(ONW-WR) th(RD-ONW), th(WR-ONW) tsu(DB-RD) th(RD-DB)
__ __ __ ____ __ ____ ____ __ ____ __ ____
ONW input hold time Data bus set up time Data bus hold time
________
ONW input set up time
_________
ONW input hold time Data bus set up time Data bus hold time
3.1.10 Switching characteristics in memory expansion mode and microprocessor mode Table 3.1.15 Switching characteristics in memory expansion and microprocessor mode (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, in high-speed mode, unless otherwise noted)
Symbol tc() tWH() tWL() td(-AH) td(-AL) tv(-AH) tv(-AL) td(-SYNC) tv(-SYNC) td(-DB) tv(-DB) tWL(RD), tWL(WR)
__ __
Parameter

Test conditions Fig. 3.1.1
Limits Min. tC(XIN)-10 tC(XIN)-10 16 20 2 2 5 5 16 5 15 10 tC(XIN)-10 3tC(XIN)-10 tC(XIN)-35 tC(XIN)-40 2 2 tC(XIN)-16 tC(XIN)-20 5 5 15 10 200 0 100 30 30 35 40 Typ. 2tC(XIN) Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
clock cycle time clock "H" pulse width clock "L" pulse width
AD15-AD8 delay time AD7-AD0 delay time AD15-AD8 valid time AD7-AD0 valid time SYNC delay time SYNC valid time Data bus delay time Data bus valid time
__ __ ___ ___
RD pulse width, WR pulse width RD pulse width, WR pulse width (When one-wait is valid)
td(AH-RD), td(AH-WR) td(AL-RD), td(AL-WR) tv(RD-AH), tv(WR-AH) tv(RD-AL), tv(WR-AL) td(WR-DB) tv(WR-DB) td(RESET-RESETOUT) tv(-RESETOUT)
____________ _____ ____________ __ __ __ __ __ __ __ __
__
__
AD15-AD8 delay time AD7-AD0 delay time AD15-AD8 valid time AD7-AD0 valid time Data bus delay time Data bus valid time
_______________
RESETOUT output delay time
_______________
RESETOUT output valid time (Note)
Note: ____________ The RESETOUT output goes "H" in sync with the fall of the clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes "H".
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3.1 Electrical characteristics
Measurement output pin 100pF Measurement output pin
1k
100pF CMOS output N-channel open-drain output
Fig. 3.1.1 Circuit for measuring output switching characteristics (1)
Fig. 3.1. 2 Circuit for measuring output switching characteristics (2)
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3.1 Electrical characteristics
Timing Diagram
tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2VCC
CNTR 0, CNTR 1
0.8VCC
tWH(INT)
tWL(INT) 0.2VCC
INT0 INT4
0.8VCC
tW(RESET)
RESET
0.2VCC
0.8VCC
tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC
XIN
0.8VCC
tf
tWL(SCLK1), tWL(SCLK2) 0.2VCC
tC(SCLK1), tC(SCLK2) tr 0.8VCC
tWH(SCLK1), tWH(SCLK2)
SCLK1 SCLK2
tsu(RXD-SCLK1), tsu(SIN2-SCLK2)
th(SCLK1-RXD), th(SCLK2-SIN2),
RXD SIN2
0.8VCC 0.2VCC td(SCLK1-TXD),td(SCLK2-SOUT2) tv(SCLK1-TXD), tv(SCLK2-SOUT2)
TXD SOUT2
Fig. 3.1.3 Timing diagram (1) (in single-chip mode)
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3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode(CMOS level input)
tC( tWH( 0.5VCC td(
-AH) )
)
tWL(
)
tv( 0.5VCC
-AH)
AD15 AD8
td(
-AL)
tv( 0.5VCC
-AL)
AD7 AD0
td(
-SYNC)
tv( 0.5VCC td(
-WR)
-SYNC)
SYNC
tv(
-WR)
RD,WR
tSU(ONW)
0.5VCC th(
-ONW)
ONW
0.8VCC 0.2VCC
tSU(DB-
)
th(
-DB)
DB0 DB7 (At CPU reading) DB0 DB7 (At CPU writing)
0.8VCC 0.2VCC td(
-DB)
tv( 0.5VCC
-DB)
Timing Diagram in Microprocessor Mode RESET
0.8VCC
0.2VCC
0.5VCC td(RESET- RESETOUT) tv(
-RESETOUT)
RESETOUT
0.5VCC
Fig. 3.1.4 Timing diagram (2) (in memory expansion mode and microprocessor mode)
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APPENDIX
3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode(CMOS level input)
tWL(RD) tWL(WR)
RD,WR
td(AH-RD) td(AH-WR)
0.5VCC
tv(RD-AH) tv(WR-AH)
AD15 AD8
0.5VCC
td(AL-RD) td(AL-WR)
tv(RD-AL) tv(WR-AL)
AD7 AD0
0.5VCC
tsu(ONW-RD) tsu(ONW-WR)
th(RD-ONW) th(WR-ONW)
ONW (At CPU reading) RD
0.8VCC 0.2VCC
0.5VCC
tSU(DB-RD)
th(RD-DB)
DB0 DB7 (At CPU writing) WR
td(WR-DB)
0.5VCC
0.8VCC 0.2VCC
tv(WR-DB)
0.5VCC
DB0 DB7
Fig. 3.1.5 Timing diagram (3) (in memory expansion mode and microprocessor mode)
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3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode(TTL level input)
tC( tWH(
2.0V 0.8V
) )
tWL(
)
td(
-AH)
tv(
2.0V 0.8V
-AH)
AD15 AD8
td(
-AL)
tv(
2.0V 0.8V
-AL)
AD7 AD0
td( t
-SYNC)
tv(
-SYNC)
SYNC
2.0V 0.8V
td(
-WR)
tv(
-WR)
RD,WR
tSU(ONW)
2.0V 0.8V
th(
-ONW)
ONW
2.0V 0.45V
tSU(DB-
)
th(
-DB)
DB0 DB7 (At CPU reading) DB0 DB7 (At CPU writing)
2.0V 0.45V
td(
-DB)
tv(
2.0V 0.8V
-DB)
Timing Diagram in Microprocessor Mode RESET
0.8VCC 0.2VCC
2.0V 0.8V
td(RESET-RESETOUT)
tv(
-RESETOUT)
RESETOUT
2.0V 0.8V
Fig. 3.1.6 Timing diagram (4) (in memory expansion mode and microprocessor mode)
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3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode(TTL level input)
tWL(RD) tWL(WR)
RD,WR
td(AH-RD) td(AH-WR)
2.0V 0.8V
tv(RD-AH) tv(WR-AH)
AD15 AD8
2.0V 0.8V
td(AL-RD) td(AL-WR)
tv(RD-AL) tv(WR-AL)
AD7 AD0
2.0V 0.8V
tsu(ONW-RD) tsu(ONW-WR)
th(RD-ONW) th(WR-ONW)
ONW
2.4V 0.45V
(At CPU reading)
RD
2.0V 0.8V
tSU(DB-RD)
th(RD-DB)
DB0 DB7
2.4V 0.45V
(At CPU writing)
WR
2.0V 0.8V
td(WR-DB)
tv(WR-DB)
2.0V 0.8V
DB0 DB7
Fig. 3.1.7 Timing diagram (5) (in memory expansion mode and microprocessor mode)
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3.2 Standard characteristics
3.2 Standard characteristics
3.2.1 Power source current characteristic examples Figures 3.2.1 and Figure 3.2.2 show power source current characteristic examples.
[Measuring condition : 25 C, f(XCIN) = 32kHz, A-D conversion operatting, in high-speed mode]
Rectangular waveform
Power source current (mA)
10 9 8 7 6 5 4 3 2 1 0
Vcc=5.0V, Ta=25C
0
1
2
3
4
5
6
7
8
9
10
Frequency f(XIN)(MHz)
Fig. 3.2.1 Power source current characteristic example
[Measuring condition : 25 C, f(XCIN) = 32kHz, A-D conversion operatting, in high-speed mode]
Rectangular waveform
Power source current 1.0 (mA)
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
Vcc=5.0V, Ta=25C
0
1
2
3
4
5
6
7
8
9
10
Frequency f(XIN)(MHz)
Fig. 3.2.2 Power source current characteristic example (in wait mode)
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APPENDIX
3.2 Standard characteristics
3.2.2 Port standard characteristic examples Figures 3.2.3, Figure 3.2.4, Figure 3.2.5, and Figure 3.2.6 show port standard characteristic examples.
[Port P87 IOH-VOH characteristic (P-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P60--P62, P65, P7, P8, CMPOUT)
IO H (mA)
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0
Vcc=5.5V,Ta=90C Vcc=5.0V,Ta=90C Vcc=3.0V,Ta=90C 1 2
3
4
5
6 VOH (V)
Fig. 3.2.3 Standard characteristic example of CMOS output port at P-channel drive (1)
[Port P87 IOH-VOH characteristic (P-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P60--P62, P65, P7, P8, CMPOUT)
IO H (mA) -100 -90 -80 -70 -60 -50 -40 -30 -20
Vcc=5.5V,Ta=25C
Vcc=5.0V,Ta=25C
-10
Vcc=3.0V,Ta=25C
0
0
1
2
3
4
5
6
VOH (V)
Fig. 3.2.4 Standard characteristic example of CMOS output port at P-channel drive (2)
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3.2 Standard characteristics
[Port P87 IOL-VOL characteristic (N-channel drive)] (Pins with same characteristic : P0, P1, P20--P23, P3, P4, P5, P60--P62, P65, P7, P8, CMPOUT, P24--P27 except in single-chip mode)
IOL (mA) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 1 2 3 4 5 6 VOL (V) Vcc=3.0V,Ta=90C Vcc=5.5V,Ta=90C Vcc=5.0V,Ta=90C
Fig. 3.2.5 Standard characteristic example of CMOS output port at N-channel drive (1)
[Port P87 IOL-VOL characteristic (N-channel drive)] (Pins with same characteristic : P0, P1, P20--P23, P3, P4, P5, P60--P62, P65, P7, P8, CMPOUT, P24--P27 except in single-chip mode)
IOL (mA) -100 -90 -80 -70 -60 -50 -40 -30 Vcc=3.0V,Ta=25C -20 -10 0 0 1 2 3 4 5 6 VO L (V) Vcc=5.5V,Ta=25C Vcc=5.0V,Ta=25C
Fig. 3.2.6 Standard characteristic example of CMOS output port at N-channel drive (2)
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APPENDIX
3.2 Standard characteristics
[Port P27 IOL-VOL characteristic (N-channel drive)] (Pins with same characteristic : P24--P27 in single-chip mode)
IOL (mA) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 1 2 3 4 5 6 VOL (V) Vcc=3.0V,Ta=90C Vcc=5.5V,Ta=90C Vcc=5.0V,Ta=90C
Fig. 3.2.7 Standard characteristic example of CMOS output port at N-channel drive (4)
[Port P27 IOL-VOL characteristic (N-channel drive)] (Pins with same characteristic : P24--P27 in single-chip mode)
IOL (mA) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 1 2 3 4 5 6 VOL (V) Vcc=3.0V,Ta=25C
Vcc=5.5V,Ta=25C Vcc=5.0V,Ta=25C
Fig. 3.2.8 Standard characteristic example of CMOS output port at N-channel drive (5)
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3.2 Standard characteristics
3.2.3 Input current standard characteristic examples Figure 3.2.9 and Figure 3.2.10 show input current standard characteristic examples.
[Port P27 IIL characteristic (at pull-up)] (Pins with same characteristic : P0, P1, P2)
IIL (mA) -250 -225 -200 -175 -150 -125 -100 -75 -50 -25 0 0 Vcc=3.0V,Ta=90C 1 2 3 4 5 6 VI (V) Vcc=5.0V,Ta=90C Vcc=5.5V,Ta=90C
Fig. 3.2.9 Standard characteristic example of input current at connecting pull-up transistor (1)
[Port P27 IIL characteristic (at pull-up)] (Pins with same characteristic : P0, P1, P2)
IIL (mA) -250 -225 -200 -175 -150 -125 -100 -75 -50 -25 0 0 1 2 3 4 5 6 VI (V) Vcc=3.0V,Ta=25C Vcc=5.0V,Ta=25C Vcc=5.5V,Ta=25C
Fig. 3.2.10 Standard characteristic example of input current at connecting pull-up transistor (2)
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APPENDIX
3.2 Standard characteristics
3.2.4 A-D conversion standard characteristics Figure 3.2.11 shows the A-D conversion standard characteristics. The lower-side line on the graph indicates the absolute precision error. It represents the deviation from the ideal value. For example, the conversion of output code from 0 to 1 occurs ideally at the point of AN0 = 10 mV, but the measured value is 0 mV. Accordingly, the measured point of conversion is represented as "10 - 0 = 10 mV." The upper-side line on the graph indicates the width of input voltages equivalent to output codes. For example, the measured width of the input voltage for output code 13 is 22 mV, so the differential nonlinear error is represented as "22 - 20 = 2 mV" (0.1 LSB).
A-D CONVERTER STEP WIDTH MEASUREMENT
Measured when a power source voltage is stable in the single-chip mode and the high-speed mode Fig. 3.2.11 A-D conversion standard characteristics
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3.2 Standard characteristics
3.2.5 D-A conversion standard characteristics Figure 3.2.12 shows the D-A conversion standard characteristics. The lower-side line on the graph indicates the absolute precision error. In this case, it represents the difference between the ideal analog output value for an input code and the measured value. The upper-side line on the graph indicates the change width of output analog value to a one-bit change of input code.
D-A CONVERTER STEP WIDTH MEASUREMENT
Measured when a power source voltage is stable in the single-chip mode and the high-speed mode Fig. 3.2.12 D-A conversion standard characteristics
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APPENDIX
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on interrupts (1) Sequence for switching an external interrupt detection edge When the external interrupt detection edge must be switched, make sure the following sequence. Reason The interrupt circuit recognizes the switching of the detection edge as the change of external input signals. This may cause an unnecessary interrupt. Clear an interrupt enable bit to "0" (interrupt disabled) Switch the detection edge Clear an interrupt request bit to "0" (no interrupt request issued) Set the interrupt enable bit to "1" ( interrupt enabled )
(2) Bit 7 of the interrupt control register 2 Fix the bit 7 of the interrupt control register 2 (Address:003F16) to "0". Figure 3.3.1 shows the structure of the interrupt control register 2.
b7
b0 Interrupt control register 2 Address 003F16
0
Interrupt enable bits Not used Fix this bit to "0"
Fig. 3.3.1 Structure of interrupt control register 2 3.3.2 Notes on the serial I/O1 (1) Stop of data transmission As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the transmit enable bit to "0" (transmit disabled), and clear the serial I/O enable bit to "0" (serial I/O1 disabled)in the following cases : q when stopping data transmission during transmitting data in the clock synchronous serial I/O mode q when stopping data transmission during transmitting data in the UART mode q when stopping only data transmission during transmitting and receiving data in the UART mode Reason Since transmission is not stopped and the transmission circuit is not initialized even if the serial I/O1 enable bit is cleared to "0" (serial I/O1 disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK1, ______ and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, the data is transferred to the transmit shift register and start to be shifted. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD pin and it may cause an operation failure to a microcomputer. (2) Stop of data reception As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the receive enable bit to "0" (receive disabled), or clear the serial I/O enable bit to "0" (serial I/O disabled) in the following case : q when stopping data reception during receiving data in the clock synchronous serial I/O mode Clear the receive enable bit to "0" (receive disabled) in the following cases : q when stopping data reception during receiving data in the UART mode q when stopping only data reception during transmitting and receiving data in the UART mode
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3.3 Notes on use
(3) Stop of data transmission and reception in a clock synchronous serial I/O mode As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear both the transmit enable bit and receive enable bit to "0" (transmit and receive disabled) at the same time in the following case: q when stopping data transmission and reception during transmitting and receiving data in the clock synchronous mode (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to "0" (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to "0" (serial I/O1 disabled) (refer to (1)).
_____
(4) The SRDY pin on a receiving side _____ When signals are output from the SRDY pin on the reception_____by using an external clock in the clock side synchronous serial I/O mode, set all of the receive enable bit, the SRDY output enable bit, and the transmit enable bit to "1" (transmit enabled). (5) Stop of data reception in a clock synchronous serial I/O mode Set the serial I/O1 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to "0." Clear both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Set the bits 0 to 3 and bit 6 of the serial I/O1 control register Set both the transmit enable bit (TE) and the receive enable bit (RE) to "1"
Can be set with the LDM instruction at the same time
(6) Control of data transmission using the transmit shift completion flag The transmit shift completion flag changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When checking the transmit shift completion flag after writing a data to the transmit buffer register for controlling a data transmission, note this delay. (7) Control of data transmission using an external clock When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to "1" at "H" level of the SCLK input signal. Also, write data to the transmit buffer register at "H" level of the SCLK input signal.
3.3.3 Notes on the A-D converter (1) Input of signals from signal source with high impedance to an analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 F to 1 F. Further, make sure to check the operation of application products on the user side. Reason The A-D converter builds in the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, a charge and discharge noise generates. This may cause the A-D conversion precision to be worse.
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APPENDIX
3.3 Notes on use
(2) AVSS pin Connect a power source for the A-D converter, AVSS pin to the VSS line of the analog circuit. (3) A clock frequency during an A-D conversion The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. Thus, make sure the following during an A-D conversion. q f(XIN) is 500 kHz or more . (When the ONW pin is "L", f(XIN) is 1 MHz or more.) q Do not execute the STP instruction and WIT instruction.
3.3.4 Notes on the RESET pin When a rising time of the reset signal is long, connect a ceramic capacitor or others across the RESET pin and the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, make sure the following : qMake the length of the wiring which is connected to a capacitor the shortest possible. qMake sure to check the operation of application products on the user side. Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, a microcomputer may malfunction.
3.3.5 Notes on input and output pins (1) Fix of a port input level in stand-by state Fix input levels of an input and an I/O port for getting effect of low-power dissipation in stand-by state, especially for the I/O ports of the N-channel open-drain. Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, make sure the following: qExternal circuit qVariation of output levels during the ordinary operation * stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
Reason Even when setting as an output port with its direction register, in the following state : qN-channel......when the content of the port latch is "1" the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Make sure that the level becomes "undefined" depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input and an I/O port are "undefined." This may cause power source current. (2) Modify of the content of I/O port latch When the content of the port latch of an I/O port is modified with the bit managing instruction*, the value of the unspecified bit may be changed. Reason The bit managing instruction is read-modify-write instruction for reading and writing data by a byte unit. Accordingly, when this instruction is executed on one bit of the port latch of an I/O port, the following is executed to all bits of the port latch. qAs for a bit which is set as an input port : The pin state is read in the CPU, and is written to this bit after bit managing. qAs for a bit which is set as an output port : The bit value is read in the CPU, and is written to this bit after bit managing.
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3.3 Notes on use
Make sure the following : qEven when a port which is set as an output port is changed for an input port, its port latch holds the output data. qEven when a bit of a port latch which is set as an input port is not speccified with a bit managing instruction, its value may be changed in case where content of the pin differs from a content of the port latch. * bit managing instructions : SEB, and CLB instruction (3) The AVSS pin when not using the A-D converter When not using the A-D converter, handle a power source pin for the A-D converter, AVSS pin as follows : q AVSS : Connect to the VSS pin Reason If the AVSS pin is opened, the microcomputer may malfunction by effect of noise or others.
3.3.6 Notes on memory expansion mode and microprocessor mode (1) Writing data to the port latch of port P3 In the memory expansion or the microprocessor mode, ports P30 and P31 can be used as the output port. Use the LDM or STA instruction for writing data to the port latch (address 000616) of port P3. When using a read-modify-write instruction (the SEB or the CLB instruction), allocate the read and the write enabled memory at address 000616. Reason In the memory expansion or microprocessor mode, address 000616 is allocated in the external area. Accordingly, q Data is read from the external memory. q Data is written to both the port latch of the port P3 and the external memory. Accordingly, when executing a read-modify-write instruction for address 000616, external memory data is read and modified, and the result is written in both the port latch of the port P3 and the external memory. If the read enabled memory is not allocated at address 000616, the read data is undefined. The undefined data is modified and written to the port latch of the port P3. The port latch data of port P3 becomes "undefined." (2) Overlap of an internal memory and an external memory When the internal and the external memory are overlapped in the memory expansion mode, the internal memory is valid in this overlapped area. When the CPU writes or reads to this area, the following is performed : q When reading data Only the data in the internal memory is read into the CPU and the data in the external memory is not read into the CPU. However, as the read signal and address are still valid, the external memory data of the corresponding address is output to the external data bus. q When writing data Data is written in both the internal and the external memory.
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APPENDIX
3.3 Notes on use
3.3.7 Notes on built-in PROM (1) Programming adapter To write or read data into/from the internal PROM, use the dedicated programming adapter and general-purpose PROM programmer as shown in Table 3.3.1. Table 3.3.1 Programming adapter Microcomputer M38073E4FS M38073E4FP (one-time blank) PCA4738F-80A Programming adapter PCA4738L-80A
(2) Write and read In PROM mode, operation is the same as that of the M5M27C256AK, but programming conditions of PROM programmer are not set automatically because there are no internal device ID codes. Accurately set the following conditions for data write/read. Take care not to apply 21 V to Vpp pin (is also used as the CNVSS pin), or the product may be permanently damaged. q Programming voltage : 12.5 V q Setting of programming adapter switch : refer to table 3.3.2 q Setting of PROM programmer address : refer to table 3.3.3 Table 3.3.2 Setting of programming adapter switch Programming adapter PCA4738F-80A PCA4738L-80A Table 3.3.3 Setting of PROM programmer address Microcomputer M38073E4FS M38073E4FP Address : 408016 (Note 1) Address : 7FFD16 (Note 1) PROM programmer start address PROM programmer completion address CMOS CMOS OFF SW 1 SW 2 SW 3
Note : Addresses C08016 to FFFD16 in the internal PROM correspond to addresses 408016 to 7FFD16 in the ROM programmer. (3) Erasing Contents of the windowed EPROM are erased through an ultraviolet light source of the wavelength 2537Angstrom . At least 15 W-sec/cm 2 are required to erase EPROM contents.
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APPENDIX
3.4 Countermeasures against noise
3.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 Shortest wiring length The wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Wiring for the RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). Reason The reset works to initialize a microcomputer. The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway.
Noise
Reset circuit VSS
RESET VSS
Reset circuit VSS
RESET VSS
N.G.
3807 group
O.K.
3807 group
Fig. 3.4.1 Wiring for the RESET pin (2) Wiring for clock input/output pins qMake the length of wiring which is connected to clock I/O pins as short as possible. qMake the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. qSeparate the VSS pattern only for oscillation from other VSS patterns. Reason A microcomputer's operation synchronizes with a clock generated by the oscillator (circuit). If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a malfunction or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer.
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APPENDIX
3.4 Countermeasures against noise
Noise
An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example
XIN XOUT VSS
XIN XOUT VSS
N.G.
Fig. 3.4.2 Wiring for clock I/O pins
O.K.
Separate the VSS line for oscillation from other VSS lines
,,, ,,,, ,,,, ,,,
XIN XOUT VSS
(3) Wiring for the VPP pin of the One Time PROM version and the EPROM version (In this microcomputer the VPP pin is also used as the CNVSS pin) Connect an approximately 5 k resistor to theV P P pin the shortest possible in series and also to the VSS pin. When not connecting the resistor, make the length of wiring between the VPP pin and the VSS pin the shortest possible. Note:Even when a circuit which included an approximately 5 k resistor is used in the Mask ROM version, the maicrocomputer operates correctly. Reason The VPP pin of the One Time PROM and the EPROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for wiring flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway.
Approximately 5k CNVSS/VPP VSS
3807 group
Make it the shortest possible
Fig. 3.4.3 Wiring for the VPP pin of the One Time PROM and the EPROM version
3.4.2 Connection of a bypass capacitor across the Vss line and the Vcc line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VCC line as follows: qConnect a bypass capacitor across the VSS pin and the VCC pin at equal length . qConnect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. qUse lines with a larger diameter than other signal lines for VSS line and VCC line.
Fig. 3.4.4 Bypass capacitor across the VSS line and the VCC line 3-30
3807 GROUP USER'S MANUAL
,, ,, ,, ,, ,, ,, ,,
VCC Chip VCC VSS VSS
APPENDIX
3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins qConnect an approximately 100 to 1 k resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. qConnect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides, connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog input pin and the VSS pin at equal length. Reason Signals which is input in an analog input pin (such as an A-D converter input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. If a capacitor between an analog input pin and the Vss pin is grounded at a position far away from the Vss pin, noise on the GND line may enter a microcomputer through the capacitor. 3.4.4. Consideration for oscillator Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping an oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Keeping an oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an osillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Reason Signal lines where potential levels change frequently (such as the CNTR pin line) may affect other lines at signal rising or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway.
Noise
(Note)
Microcomputer Analog input pin
Thermistor
N.G.
O.K.
VSS
Note:The resistor is used for dividing resistance with a thermistor. Fig.3.4.5 Analog signal line and a resistor and a capacitor
Microcomputer Mutual inductance M Large current GND Fig.3.4.6 Wiring for a large current signal line XIN XOUT VSS
N.G.
Do not cross CNTR XIN XOUT VSS
Fig.3.4.7 Wiring to a signal line where potential levels change frequently 3-31
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APPENDIX
3.4 Countermeasures against noise
3.4.5 Setup for I/O ports Setup I/O ports using hardware and software as follows: qConnect a resistor of 100 or more to an I/O port inseries. qAs for an input port, read data several times by a program for checking whether input levels are equal or not. qAs for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. qRewirte data to direction registers and pull-up control registers (only the product having it) at fixed periods.
O.K.
Data bus
Direction register
Noise
Noise
N.G.
Port latch I/O port pins
Fig. 3.4.8 Setup for I/O ports
When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse. 3.4.6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
Main routine (SWDT) N CLI Main processing N (SWDT) =N? =N Interrupt processing
Interrupt processing routine (SWDT) (SWDT)--1 Interrupt processing (SWDT) 0? 0 >0 RTI Return Main routine
routine errors errors qAssigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. Fig. 3.4.9 Watchdog timer by software The initial value N should satisfy the following condition: N+1 (Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. qWatches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing count after the initial value N has been set. qDetects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following cases: If the SWDT contents do not change after interrupt processing
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APPENDIX
3.4 Countermeasures against noise
qDecrements the SWDT contents by 1 at each interrupt processing. qDetermins that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). qDetects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: When the contents of the SWDT reach 0 or less by continuative decrement without initializing to the initial value N.
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APPENDIX
3.5 List of registers
3.5 List of registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 7, 8) [Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0E16, 1016]
B 0 Port Pi0 1 Port Pi1
Name
q
Function
In output mode Write Port latch Read In input mode Write : Port latch Read : Value of pins
At reset
RW
0 0 0 0 0 0 0 0
q
2 Port Pi2 3 Port Pi3 4 Port Pi4 5 Port Pi5 6 Port Pi6 7 Port Pi7
Fig. 3.5.1 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 7, 8)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 7, 8) [Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0F16, 1116]
B
Name
Function
0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode
At reset
RW
! ! ! ! ! ! ! !
0 Port Pi direction register 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
Fig. 3.5.2 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 7, 8)
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APPENDIX
3.5 List of registers
Port P6
b7 b6 b5 b4 b3 b2 b1 b0 Port P6 (P6) [Address : 0C16]
B 0 Port P60 1 Port P61
Name
q
Function
In output mode Write Port latch Read In input mode Write : Port latch Read : Value of pins
At reset
RW
0 0 0 0 0 0 0 0 ! ! ! !
q
2 Port P62 3 Port P63 4 Port P64 5 Port P65
(Note) (Note)
6 Nothing is allocated for these bits. These are write disabled bits. 7 When these bits are read out, the values are "0".
Note : These bits are used only for input port.
Fig. 3.5.3 Structure of Port P6
Port P6 direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port P6 direction register (P6D) [Address : 0D16]
B
registers
Name
Function
0 : Port P60 input mode 1 : Port P60 output mode 0 : Port P61 input mode 1 : Port P61 output mode 0 : Port P62 input mode 1 : Port P62 output mode
At reset
RW
! ! ! ! ! ! ! !
0 Port P60--P62 direction 1 2
0 0 0 0 0 0 0 0
3 Ports P63 and P64 are input ports.
Accordingly, these bits do not have a direction register. 4 Nothing is allocated for these bits. 0 : Port P65 input mode 1 : Port P65 output mode 6 Nothing is allocated for these bits. These are write disabled bits. 7 When these bits are read out, the values are "0".
5 Port P65 direction register
Fig. 3.5.4 Structure of Port P6 direction register
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APPENDIX
3.5 List of registers
Timer XY control register
b7 b6 b5 b4 b3 b2 b1 b0 Timer XY control register (TXYCON) [Address : 1416]
B 0 1
Name
Timer X stop control bit Timer Y stop control bit
Function
0 : Start counting 1 : Stop counting
At reset
RW
1 1 0 0 0 0 0 0
! ! ! ! ! !
0 : Start counting 1 : Stop counting 2 Nothing is allocated for these bits. These are write disabled bits. 3 When these bits are read out, the values are "0."
4 5 6 7
Fig. 3.5.5 Structure of Timer XY control reigster
Port P2P3 control register
b7 b6 b5 b4 b3 b2 b1 b0 Port P2P32 control register (P2P3C) [Address : 1516]
Name B 0 P34 clock output control bit 1 Output clock frequency
selection bits
Function
0 : I/O port (P34) 1 : Clock output (CKOUT output pin)
b3 b2 b1
At reset
RW
0 0 0 0 0 0 0
(Note 2)
2 3
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0: 1 : f(XIN) 0 : "L" fixed output 1 : "L" fixed output 0 : f(XIN) (f(XCIN)) 1 : f(XIN)/2 (f(XCIN)/2) 0 : f(XIN)/4 (f(XCIN)/4) 1 : f(XIN)/16 (f(XCIN)/16) (Note 1)
4 Nothing is allocated for these bits. These are write disabled bits. 5 When these bits are read out, the values are "0." 6 7 P2*P3 input level selection bit 0 : CMOS level
1 : TTL level Note 1 : In low-speed mode ( ) is selected. 2 : When CNVss pin is connected to Vss, the value is "0". When CNVss pin is connected to Vcc, the value is "1".
! ! !
Fig. 3.5.6 Structure of Port P2P3 control register
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APPENDIX
3.5 List of registers
Pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0 Pull-up control register (PULL) [Address : 1616]
Name B 0 P00--P03 pull-up control bit 1 P04, P05 pull-up control bit 2 P06 pull-up control bit 3 P07 pull-up control bit 4 P10--P13 pull-up control bit 5 P14--P17 pull-up control bit 6 P20--P23 pull-up control bit 7 P24--P27 pull-up control bit
Note : Valid only in input mode.
Function
0 : No pull-up 1 : Pull-up (Note) 0 : No pull-up 1 : Pull-up (Note) 0 : No pull-up 1 : Pull-up (Note) 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up (Note)
At reset
RW
0 0 0 0 0
(Note)
0
(Note)
0
(Note)
0
0 : No pull-up 1 : Pull-up (Note)
Fig. 3.5.7 Structure of Pull-up control register
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer control register (WDTCON) [Address : 1716]
B Name 0 Watchdog timer H 1 2 3 4 5
Function
q After re-set a watchdog timer operates by writting any values in this register q After
At reset
RW
! ! ! ! ! !
re-set these bits are re-set to "0000002" by writting any values in this register. 0 : STP instruction enabled STP instruction disable bit 6 (Note) 1 : STP instruction disabled Watchdog timer H count 0 : Watchdog timer L underflow 7 source selection bit 1 : f(XIN)/16 or f(XCIN)/16
1 1 1 1 1 1 0 0
Note : When this bit is set to "1", it is not rewritten to "0" by software.
Fig. 3.5.8 Structure of Watchdog timer control register
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APPENDIX
3.5 List of registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 1816] Function B 0 A transmission data is written to or a receive data is read out 1 2 3 4 5 6 7
Note : A content of the Transmit buffer register cannot be read out. A data cannot be written to the Receive buffer register.
At reset
RW
from this buffer register. * At writing : a data is written to the Transmit buffer register. * At reading : a content of the Receive buffer register is read out.
? ? ? ? ? ? ? ?
Fig. 3.5.9 Structure of Transmit/Receive buffer register
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 status reigster (SIO1STS) [Address : 1916]
Name B Transmit buffer empty flag 0
(TBE)
Function
0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full 0 : Transmit shift in progress 1 : Transmit shift completed 0 : No error 1 : Overrun error 0 : No error 1 : Parity error 0 : No error 1 : Framing error 0 : (OE) (PE) (FE) = 0 1 : (OE) (PE) (FE) = 1
At reset
0 0 0 0 0 0 0 1
RW ! ! ! ! ! ! ! !
1 Receive buffer full flag (RBF) 2 Transmit shift register shift
completion flag (TSC)
3 Overrun error flag (OE) 4 Parity error flag (PE) 5 Framing error flag (FE) 6 Summing error flag (SE)
7 Nothing is allocated for this bit. It is a write disabled bit.
When this bit is read out, the value is "0."
Fig. 3.5.10 Structure of Serial I/O1 status register
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3.5 List of registers
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 control register (SIO1CON) [Address : 1A16] B 0 1
Name
BRG count source selection bit (CSS) Serial I/O1 synchronous clock selection bit (SCS) 0 : f(XIN) 1 : f(XIN)/4
Function
(Note 1) (Note 2)
At reset
RW
0 0
At selecting clock synchronous serial I/O 0 : BRG output divided by 4 1 : External clock input
At selecting UART
0 : BRG output divided by 16 1 : External clock input divided by 16
2 3
SRDY1 output enable bit
(SRDY) Transmit interrupt source selection bit (TIC) Transmit enable bit (TE) Receive enable bit (RE) Serial I/O1 mode selection bit (SIOM) Serial I/O1 enable bit (SIOE)
4 5 6 7
0 : I/O port (P47) 1 : SRDY1 output pin 0 : Transmit buffer empty 1 : Transmit shift operating completion 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : UART 1 : Clock synchronous serial I/O
0 : Serial I/O1 disabled (P44-P47 : I/O port) 1 : Serial I/O1 enabled (P44-P47 : Serial I/O function pin)
0 0
0 0 0 0
Note 1 : In low-speed mode f(XCIN) is selected. 2 : In low-speed mode f(XCIN)/4 is selected.
Fig. 3.5.11 Structure of Serial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UARTCON) [Address : 1B16]
Name B Character length 0 1 2 3 4
Function
0 : 8 bits 1 : 7 bits 0 : Parity checking disabled 1 : Parity checking enabled 0 : Even parity 1 : Odd parity 0 : 1 stop bit 1 : 2 stop bits In output mode 0 : CMOS output 1 : N-channel open-drain output
At reset
RW
0 0 0 0 0
5 6 7
selection bit (CHAS) Parity enable bit (PARE) Parity selection bit (PARS) Stop bit length selection bit (STPS) P45/TxD P-channel output disable bit (POFF) Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "1."
1 1 1
! ! !
Fig. 3.5.12 Structure of UART control register
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APPENDIX
3.5 List of registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator (BRG) [Address : 1C16]
B
Function
At reset
RW
0 A count value of Baud rate generator is set. 1 2 3 4 5 6 7
? ? ? ? ? ? ? ?
Fig. 3.5.13 Structure of Baud rate generator
Serial I/O2 control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 control register 1 (SIO2CON1) [Address : 1D16]
Name B Internal synchronous 0
clock selection bits
Function
b2 b1 b0
At reset
RW
(Note) (f(XCIN)/8) (f(XCIN)/16) (f(XCIN)/32) (f(XCIN)/64) (f(XCIN)/128) (f(XCIN)/256)
0 0 0 0 0 0 0 0
1 2 3 Serial I/O2 port selection bit 4 5 6 7
0 0 0 0 1 1
0 0 1 1 1 1
0 : f(XIN)/8 1 : f(XIN)/16 0 : f(XIN)/32 1 : f(XIN)/64 0 : f(XIN)/128 1 : f(XIN)/256
0 : I/O port (P71, P72) 1 : SOUT2, SCLK2 output pin 0 : I/O port (P73) SRDY2 output enable bit 1 : SRDY2 output pin 0 : LSB first Transfer direction selection bit 1 : MSB first Serial I/O2 synchronous clock 0 : External clock 1 : Internal clock selection bit In output mode P71/ SOUT2, P72/ SCLK2 0 : CMOS output P-channel output disable bit 1 : N-channel open-drain output
Note : In low-speed mode ( ) is selected.
Fig. 3.5.14 Structure of Serial I/O2 control register 1
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3.5 List of registers
Serial I/O2 control register 2
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 control register 2 (SIO2CON2) [Address : 1E16]
Name B Optional transfer bits 0 1 2
Function
b2 b1 b0
At reset
RW
1 1 1 0 0 0 0 0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 : 1 bit 1 : 2 bit 0 : 3 bit 1 : 4 bit 0 : 5 bit 1 : 6 bit 0 : 7 bit 1 : 8 bit
3 Nothing is allocated for these bits. These are write disabled bits. 4 When these bits are read out, the values are "0." 5 0 : P51 I/O 6 Serial I/O2 I/O comparative
signal control bit SOUT2 pin control bit (P71) 7 1 : SCMP2 output 0 : Output active 1 : Output high impedance
! ! !
Fig. 3.5.15 Structure of Serial I/O2 control register 2
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 register (SIO2) [Address : 1F16]
B
q
Function
At reset
RW
0 A shift register for serial transmission and reception.
At transmitting : Set a transmission data. q At receiving : Store a reception data. 1
? ? ? ? ? ? ? ?
2 3 4 5 6 7
Fig. 3.5.16 Structure of Serial I/O2 register
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APPENDIX
3.5 List of registers
Timer X Low-order, Timer X High-order, Timer Y Low-order, Timer Y High-order
b7 b6 b5 b4 b3 b2 b1 b0 Timer X Low-order (TXL), Timer X High-order (TXH) [Address : 2016 , 2116] Timer Y Low-order (TYL), Timer Y High-order (TYH) [Address : 2216 , 2316]
B 0 1 2
q q q
Function
A count value of each timer is set. At writing q A value set in this register is written to both a Timer and a corresponding Timer latch at the same time, or to only a Timer latch. q A value is written to low-order first. At reading q When this register is read out, a value (count value) of a corresponding Timer is read out. q A measurement value is read out in pulse period measurement mode and pulse width measurement mode. q A value is read out from high-order first.
At reset
RW
1 1 1 1 1 1 1 1
3 4 5 6 7
Fig. 3.5.17 Structure of Timer X Low-order, Timer X High-order, Timer Y Low-order, Timer Y High-order
Timer 1, Timer 3
b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 (T1), Timer 3 (T3) [Address : 2416, 2616]
B 0 1 2 3 4 5 6 7
Function
q q q
At reset
RW
A count value of each Timer is set. A value set in this register is written to both each Timer and a corresponding Timer latch at the same time. When this register is read out, a value (count value) of a corresponding Timer is read out.
1 1 1 1 1 1 1 1
Fig. 3.5.18 Structure of Timer 1, Timer 3
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3.5 List of registers
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2) [Address : 2516]
B 0 1 2 3 4 5 6 7
Function
q q
At reset
RW
q
A count value of Timer 2 is set. A value set in this register is written to both Timer 2 and a corresponding Timer 2 latch at the same time, or to only Timer 2 latch. When this register is read out, a value (count value) of a corresponding Timer 2 is read out.
1 0 0 0 0 0 0 0
Fig. 3.5.19 Structure of Timer 2
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APPENDIX
3.5 List of registers
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TXM) [Address : 2716]
B 0
Name
Timer X operating mode bits
b2 b1 b0
Function
0 0 0 0 1 0 : Timer * Event counter mode 1 : Pulse output mode 0 : Pulse period measurement mode 1 : Pulse width measurement mode 0 : Programmable waveform generation mode 1 0 1 : Programmable one-shot generation mode 1 1 0 : PWM mode 1 1 1 : Not available 0 : To a latch and a timer at the same time 1 : To only latch 0 : "L" output 1 : "H" output It depends on the operating mode of the Timer X (refer to Table 3.5.1).
b7 b6
At reset
RW
1
0 0 1 1 0
0
0
2 3 4 5
Timer X write control bit Output level latch CNTR0 active edge switch bit
0 0 0 0 0 0
Timer X count source selection 0 0 1 7 1
6 bits
0: 1: 0: 1:
f(XIN)/2 f(XIN)/16 f(XCIN) Input signal from CNTR0 pin
Fig. 3.5.20 Structure of Timer X mode register
Timer Y mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer Y mode register (TYM) [Address : 2816]
B 0
Name
Timer Y operating mode bits
b2 b1 b0
Function
0 0 0 0 1 0 : Timer * Event counter mode 1 : Pulse output mode 0 : Pulse period measurement mode 1 : Pulse width measurement mode 0 : Programmable waveform generation mode 1 0 1 : Programmable one-shot generation mode 1 1 0 : PWM mode 1 1 1 : Not available 0 : To a latch and a timer at the same time 1 : To only latch 0 : "L" output 1 : "H" output It depends on the operating mode of the Timer Y (refer to Table 3.5.1).
b7 b6
At reset
RW
1
0 0 1 1 0
0
0
2 3 4 5
Timer Y write control bit Output level latch CNTR1 active edge switch bit
0 0 0 0 0 0
Timer Y count source selection 0 0 1 7 1
6 bits
0: 1: 0: 1:
f(XIN)/2 f(XIN)/16 f(XCIN) Input signal from CNTR1 pin
Fig. 3.5.21 Structure of Timer Y mode register
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3.5 List of registers
Table. 3.5.1 Function of CNTR0/CNTR1 edge switch bit Operating mode of Timer X/Timer Y Timer mode Function of CNTR0/CNTR1 edge switch bit (bit 5 of each address 2716 and 2816) Generation of CNTR0/CNTR1 interrupt request : Falling edge (No effect on timer count) Generation of CNTR0/CNTR1 interrupt request : Rising edge (No effect on timer count) Timer X/Timer Y : Count at rising edge Generation of CNTR0/CNTR1 interrupt request : Falling edge Timer X/Timer Y : Count at falling edge Generation of CNTR0/CNTR1 interrupt request : Rising edge Start of pulse output : From "H" level Generation of CNTR0/CNTR1 interrupt request : Falling edge Start of pulse output : From "L" level Generation of CNTR0/CNTR1 interrupt request : Rising edge Timer X/Timer Y : Measurement of a period between a falling edge and the next falling edge Generation of CNTR0/CNTR1 interrupt request : Falling edge Timer X/Timer Y : Measurement of a period between a rising edge and the next rising edge Generation of CNTR0/CNTR1 interrupt request : Rising edge Timer X/Timer Y : Measurement of "H" level width Generation of CNTR0/CNTR1 interrupt request : Falling edge Timer X/Timer Y : Measurement of "L" level width Generation of CNTR0/CNTR1 interrupt request : Rising edge Timer X/Timer Y : Start of a pulse output at "L" level, and output of an one-shot "H" level pulse Generation of CNTR0/CNTR1 interrupt request : Falling edge Timer X/Timer Y : Start of a pulse output at "H" level, and output of an one-shot "L" level pulse Generation of CNTR0/CNTR1 interrupt request : Rising edge
"0" "1"
* * * * * * * * * * * * *
Event counter mode
"0" "1"
Pulse output mode
"0" "1"
Pulse period measurement mode "0"
"1" Pulse width measurement mode * * * * * * * * "1" *
"0" "1"
Programmable one-shot generation mode
"0"
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APPENDIX
3.5 List of registers
Timer 123 mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 123 mode register (T123M) [Address : 2916]
B
Name
Function
At reset
RW
TOUT output active edge switch 0 : Start at outputting "H" signal 0 bit 1 : Start at outputting "L" signal TOUT output control bit 0 : Disabled TOUT output 1 1 : Enabled TOUT output Timer 2 write control bit 0 : To a latch and a timer at the same time 2 1 : To only latch Timer 2 count source selection 0 : Output signal from Timer 1 3 bit 1 : f(XIN)/16 (Note 1) Timer 3 count source selection 0 : Output signal from Timer 1 1 : f(XIN)/16 (Note 1) b6 b5 Timer 1 count source selection 0 0 : f(XIN)/16 (Note 1) 5 bit 0 1 : f(XIN)/2 (Note 2)
0 0 0 0 0 0 0 0
!
4 bit
1 0 : f(XCIN) 1 1 : Not available Nothing is allocated for this bit. It is a write disabled bit. 7 When this bit is read out, the value is "0." Note 1 : In low-speed mode f(XCIN)/16 is selected. 2 : In low-speed mode f(XCIN)/2 is selected.
6
Fig. 3.5.22 Structure of Timer 123 mode register
Real time port register
b7 b6 b5 b4 b3 b2 b1 b0 Real time port register (RTP) [Address : 2A16]
B 0 1 2 3 4 5 6 7
Function
q q
At reset
RW
q
Sets the data to be output to the Real time port. Makes it possible to write data into any of Real time port registers 0 to 7 by specifying the Real time port data pointer (R/W pointer) and writing data into this register. Makes it possible to read any data of Real time port registers 0 to 7 by specifying the Real time port data pointer (R/W pointer) and reading data from this register.
0 0 0 0 0 0 0 0
Fig. 3.5.23 Structure of Real time port register
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3.5 List of registers
Real time port control register 0
b7 b6 b5 b4 b3 b2 b1 b0 Real time port control register 0 (RTPCON0) [Address : 2B16]
B
Name
Function
At reset
RW
(Note 1) Timer A, Timer B count source 0 : f(XIN)/2 0 selection bit 1 : f(XIN)/16 (Note 2) Real time port * port allocation 0 : 4-4 division (Corresponding ports to the Timer A : selection bit P82-P85 Corresponding ports to the Timer B : P86, P87, P30, P31) 1 1 : 2-6 division (Corresponding ports to the Timer A : P82-P87 Corresponding ports to the Timer B : P30, P31) Timer A start trigger selection bit 0 : Internal trigger (occurs by writing "1" to bit 3.) 1 : External trigger (occurs by inputting trigger to the INT4 pin.) (Note 3) 0 : No operating by writing "0" 1 : Timer A starts counting by writing "1" (when bit 2 is set to "0") 0 : Operating (is set to "0" automatically at generating a start trigger.) 1 : Stop 0 : Internal trigger (occurs by writing "1" to bit 6.) 1 : External trigger (occurs by inputting trigger to the INT4 pin.) (Note 3) 0 : No operating by writing "0" 1 : Timer B starts counting by writing "1" (when bit 5 is set to "0") 0 : Operating (is set to "0" automatically at generating a start trigger.) 1 : Stop
0
0
2
0
(Note 4)
Timer A start trigger bit
3
Timer A count source stop bit
0
(Note 4)
4
Timer B start trigger selection bit
1
5
0
(Note 4)
Timer B start trigger bit
6
Timer B count source stop bit
0
(Note 4)
7
1
Note 1: In low-speed mode f(XCIN)/2 is selected. 2: In low-speed mode f(XCIN)/16 is selected. 3: The rising edge or falling edge of the external trigger is switched by the INT4 interrupt edge selection bit (bit 4) of the interrupt edge selection register (Address : 3A16.) (However, when the One-shot pulse generation mode is selected, a rising/falling double edge trigger is generated in spite of the contents of the INT4 interrupt edge selection bit.) 4: At a read operation, "0" is always read out.
Fig. 3.5.24 Structure of Real time port control register 0
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APPENDIX
3.5 List of registers
Real time port control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Real time port control register 1 (RTPCON1) [Address : 2C16]
B
Name
b1 b0
Function
At reset
RW
Timer A operating mode 0 selection bits
1 2
3
4 5 6 7
0 0 : 8-repeated load mode 0 1 : 6-repeated load mode 1 0 : 5-repeated load mode 1 1 : One-shot pulse generation mode Real time port data pointer A 0 : R/W pointer switch bit (Note 1) 1 : Output pointer 0 : Interrupts occur when a Real Timer A interrupt mode time port output pointer value selection bit becomes "0002." 1 : Interrupt request occurs in spite of a Real time port output pointer value. Real time port data pointer A b6 b5 b4 0 0 0 : Real time port register 0 0 0 1 : Real time port register 1 0 1 0 : Real time port register 2 0 1 1 : Real time port register 3 1 0 0 : Real time port register 4 1 0 1 : Real time port register 5 1 1 0 : Real time port register 6 (Note 2) 1 1 1 : Real time port register 7 Timer A write pointer 0 : Specify the Timer A0 latch 1 : Specify the Timer A1 latch
0 0 0
0
1 1 1 1
Note 1: Use LDM or STA instruction for specifying the Real time port data pointer A when this bit is switched. When this bit is read, "1" is always read out. 2: When these bits are read, an output pointer is read out.
Fig. 3.5.25 Structure of Real time port control register 1
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3807 GROUP USER'S MANUAL
APPENDIX
3.5 List of registers
Real time port control register 2
b7 b6 b5 b4 b3 b2 b1 b0 Real time port control register 2 (RTPCON2) [Address : 2D16]
B
Name
b1 b0
Function
At reset
RW
Timer B operating mode 0 selection bits
1 2
3
4 5 6 7
0 0 : 8-repeated load mode 0 1 : 6-repeated load mode 1 0 : 5-repeated load mode 1 1 : One-shot pulse generation mode Real time port data pointer B 0 : R/W pointer switch bit (Note 1) 1 : Output pointer 0 : Interrupts occur when a Real Timer B interrupt mode time port output pointer value selection bit becomes "0002." 1 : Interrupt request occurs in spite of a Real time port output pointer value. Real time port data pointer B b6 b5 b4 0 0 0 : Real time port register 0 0 0 1 : Real time port register 1 0 1 0 : Real time port register 2 0 1 1 : Real time port register 3 1 0 0 : Real time port register 4 1 0 1 : Real time port register 5 1 1 0 : Real time port register 6 (Note 2) 1 1 1 : Real time port register 7 Timer B write pointer 0 : Specify the Timer B0 latch 1 : Specify the Timer B1 latch
0 0 0
0
1 1 1 1
Note 1: Use LDM or STA instruction for specifying the Real time port data pointer B when this bit is switched. When this bit is read, "1" is always read out. 2: When these bits are read, an output pointer is read out.
Fig. 3.5.26 Structure of Real time port control register 2
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APPENDIX
3.5 List of registers
Real time port control register 3
b7 b6 b5 b4 b3 b2 b1 b0 Real time port control register 3 (RTPCON3) [Address : 2E16]
B 0 bit (P82) 1 bit (P83) 2 bit (P84) 3 bit (P85) 4 bit (P86) 5 bit (P87) 6 bit (P30) 7 bit (P31)
Name
Function
At reset
RW
Real time port output selection 0 : I/O port 1 : Real time output port Real time port output selection Real time port output selection Real time port output selection Real time port output selection Real time port output selection Real time port output selection Real time port output selection
0 0 0 0 0 0 0 0
Fig. 3.5.27 Structure of Real time port control register 3
Timer A Low-order, Timer A High-order, Timer B Low-order, Timer B High-order
b7 b6 b5 b4 b3 b2 b1 b0 Timer A Low-order (TAL), Timer A High-order (TAH) [Address : 2F16 , 3016] Timer B Low-order (TBL), Timer B High-order (TBH) [Address : 3116 , 3216]
B 0 1 2 3 4 5 6 7
Function
q q
At reset
RW
q
Sets the real time output cycle. Writing is performed in the order of low-order and high-order. There are 2 reload latches. When the high-order side is written, the next latch is automatically specified. The latch to be written first can be specified by the Timer A or B write pointer (bit 7 of address 2C16 or 2D16). Reading is performed in the order of high-order and low-order. At a read operation, the value being counted is read out.
1 1 1 1 1 1 1 1
Fig. 3.5.28 Structure of Timer A Low-order, Timer A High-order, Timer B Low-order, Timer B High-order 3-50
3807 GROUP USER'S MANUAL
APPENDIX
3.5 List of registers
D-A control register
b7 b6 b5 b4 b3 b2 b1 b0 D-A control register (DACON) [Address : 3316]
Name B DA1 output enable bit 0 1 2 3 4 5 6 7
Function
At reset
RW
0 : Output disable (P56) 1 : Output enable (DA1 output pin) DA2 output enable bit 0 : Output disable (P57) 1 : Output enable (DA2 output pin) 0 : Output disable (P80) DA3 output enable bit 1 : Output enable (DA3 output pin) 0 : Output disable (P81) DA4 output enable bit 1 : Output enable (DA4 output pin) Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0."
0 0 0 0 0 0 0 0
! ! ! !
Fig. 3.5.29 Structure of D-A control register
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (ADCON) [Address : 3416]
B
Name
b3 b2 b1 b0
Function
0 0 0 0 : P73/SRDY2/ADT/AN0 0 0 0 1 : P74/AN1 0 0 1 0 : P75/AN2 0 0 1 1 : P76/AN3 0 1 0 0 : P77/AN4 0 1 0 1 : P60/AN5 0 1 1 0 : P61/AN6 0 1 1 1 : P62/AN7 1 0 0 0 : P63/CMPIN/AN8 1 0 0 1 : P64/CMPREF/AN9 1 0 1 0 : P65/DAVREF/AN10 1 0 1 1 : P80/DA3/AN11 1 1 0 0 : P81/DA4/AN12 When A-D trigger is invalid 0:Start conversion by writing to "0" 1:Conversion completed When A-D trigger is valid 0:Conversion in progress 1:Conversion completed 0:Connect only at A-D conversion 1:Connect all time 0 : A-D external tirgger invalid 1 : A-D external tirgger valid 0 : At conversion completed 1 : At ADT falling input
At reset
RW
0 Analog input pin selection bits
0
1
0
2
0
3 4 AD conversion completion bit
0
1
5 ADVREF input switch bit 6 AD external trigger valid bit 7 Interrupt source selection bit
0 0 0
Fig. 3.5.30 Structure of A-D control register
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APPENDIX
3.5 List of registers
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion register (AD) [Address : 3516]
B Function 0 The read-only register which A-D conversion results are stored. 1 2 3 4 5 6 7 Fig. 3.5.31 Structure of A-D conversion register
At reset
RW
! ! ! ! ! ! ! !
? ? ? ? ? ? ? ?
D-Ai conversion register
b7 b6 b5 b4 b3 b2 b1 b0 D-Ai conversion register (DAi) (i = 1, 2, 3, 4) [Address : 3616, 3716, 3816, 3916]
B Function 0 1. A value which is set to this register is converted 1 (D-A conversion). 2 2. The converted value is output from a corresponding DAi pin. 3 4 5 6 7 Fig. 3.5.32 Structure of D-Ai conversion register (i=1, 2, 3, 4)
At reset
RW
0 0 0 0 0 0 0 0
3-52
3807 GROUP USER'S MANUAL
APPENDIX
3.5 List of registers
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address : 3A16]
Name B 0 INT0 interrupt edge
selection bit
Function
0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : INT2 interrupt 1 : Timer 1 interrupt
At reset
RW
0 0 0 0 0 0 0 0
1 INT1 interrupt edge
selection bit INT2 interrupt edge 2 selection bit 3 INT3 interrupt edge selection bit
4 INT4 interrupt edge
selection bit Timer 1/INT2 interrupt 5 source bit 6 Timer 2/INT3 interrupt source bit
0 : INT3 interrupt 1 : Timer 2 interrupt
0 : INT4 interrupt 1 : Timer 3 interrupt
7 Timer 3/INT4 interrupt
source bit
Fig. 3.5.33 Structure of Interrupt edge selection register
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Address : 3B16]
B 0 1 2 3 4 5
Name
Processor mode bits
b1 b0
Function
0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor 1 1 : Not available 0 : 0 page 1 : 1 page 0 : Low 1 : High 0 : I/O port function 1 : XCIN-XCOUT operating function 0 : Operating 1 : Stopped 0 0 1 1
b7 b6
At reset
RW
0 0
(Note)
Stack page selection bit XCOUT drivability selection bit Port Xc switch bit Main clock (XIN-XOUT) stop bit Main clock division ratio
0 1 0 0 1 0
6 selection bits 7
0 : = f(XIN)/2 (high-speed mode) 1 : = f(XIN)/8 (middle-speed mode) 0 : = f(XCIN)/2 (low-speed mode) 1 : Not available
Note : An initial value of bit 1 is determined by a level of the CNVss pin.
Fig. 3.5.34 Structure of CPU mode register
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APPENDIX
3.5 List of registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 1 (IREQ1) [Address : 3C16]
B
Name
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T T T
0 INT0 interrupt request bit 1 INT1 interrupt request bit 2 Serial I/O1 receive interrupt
request bit 3 Serial I/O1 transmit interrupt request bit
0 0 0 0 0 0 0 0
4 Timer X interrupt request bit 5 Timer Y interrupt request bit
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 6 Timer 2/INT3 interrupt request 1 : Interrupt request bit Timer 3/INT4 interrupt request 0 : No interrupt request 7 1 : Interrupt request bit T "0" is set by software, but not "1."
Fig. 3.5.35 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 2 (IREQ2) [Address : 3D16]
Name B CNTR0 interrupt request bit 0 1 2 3 4 5 6 7
Function
At reset
RW
T T T T T T T !
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request CNTR1 interrupt request bit 1 : Interrupt request Serial I/O2 interrupt request bit 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request Timer 1/INT2 interrupt 1 : Interrupt request request bit 0 : No interrupt request Timer A interrupt request bit 1 : Interrupt request 0 : No interrupt request Timer B interrupt request bit 1 : Interrupt request 0 : No interrupt request ADT/AD conversion 1 : Interrupt request interrupt request bit Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0."
0 0 0 0 0 0 0 0
T "0" is set by software, but not "1."
Fig. 3.5.36 Structure of Interrupt request register 2
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3807 GROUP USER'S MANUAL
APPENDIX
3.5 List of registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E16]
B
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 INT0 interrupt enable bit 1 INT1 interrupt enable bit 2 Serial I/O1 receive interrupt
enable bit Serial I/O1 transmit interrupt 3 enable bit
0 0 0 0 0 0 0 0
4 Timer X interrupt enable bit 5 Timer Y interrupt enable bit 6 Timer 2/INT3 interrupt enable
bit Timer 3/INT4 interrupt enable 7 bit
Fig. 3.5.37 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
Name B 0 CNTR0 interrupt enable bit
Function
At reset
RW
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 CNTR1 interrupt enable bit 1 : Interrupt enabled 2 Serial I/O2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled
0 0 0 0 0 0 0 0
3 Timer 1/INT2 interrupt enable
bit 4 Timer A interrupt enable bit
5 Timer B interrupt enable bit 6 ADT/AD conversion interrupt
enable bit Fix this bit to "0." 7
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
Fig. 3.5.38 Structure of Interrupt control register 2
3807 GROUP USER'S MANUAL
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APPENDIX
3.6 Mask ROM ordering method
3.6 Mask ROM ordering method
GZZ-SH11-00B<68A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M38073M4-XXXFP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
)
g 1. Confirmation Specify the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM EPROM type (indicate the type used)
(hexadecimal notation)
27256
EPROM address 000016 Product name 000F16 001016 407F16 408016 7FFD16 7FFE16 7FFF16
ASCII code : `M38073M4-'
27512
EPROM address 000016 Product name 000F16 001016 C07F16 C08016 FFFD16 FFFE16 FFFF16
ASCII code : `M38073M4-'
In the address space of the microcomputer, the internal ROM area is from address C08016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16.
data ROM 16254 bytes
data ROM 16254 bytes
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38073M4-" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `8' = 3816 `0' = 3016 `7' = 3716 `3' = 3316 `M' = 4D16 `4' = 3416
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-56
3807 GROUP USER'S MANUAL
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH11-00B<68A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38073M4-XXXFP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27256 *= $8000 .BYTE `M38073M4-' 27512 *= $0000 .BYTE `M38073M4-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (80P6N for M38073M4-XXXFP) and attach it to the mask ROM confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator External clock input At what frequency? Quartz crystal Other ( f(XIN) = ) MHz
(2) Which function will you use the pins P41/XCIN and P40/XCOUT as P41 and P40, or XCIN and XCOUT? Ports P41 and P40 function XCIN and XCOUT function (external resonator)
g 4. Comments
(2/2)
3807 GROUP USER'S MANUAL
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APPENDIX
3.7 Mark specification form
3-58
3807 GROUP USER'S MANUAL
APPENDIX
3.8 Package outline
3.8 Package outline
3807 GROUP USER'S MANUAL
3-59
APPENDIX
3.9 Machine instructions
3.9 Machine instructions
Addressing mode Symbol Function Details IMP OP n ADC (Note 1) (Note 5) When T = 0 AA+M+C When T = 1 M(X) M(X) + M + C Adds the carry, accumulator and memory contents. The results are entered into the accumulator. Adds the contents of the memory in the address indicated by index register X, the contents of the memory specified by the addressing mode and the carry. The results are entered into the memory at the address indicated by index register X. "AND's" the accumulator and memory contents. The results are entered into the accumulator. "AND's" the contents of the memory of the address indicated by index register X and the contents of the memory specified by the addressing mode. The results are entered into the memory at the address indicated by index register X. Shifts the contents of accumulator or contents of memory one bit to the left. The low order bit of the accumulator or memory is cleared and the high order bit is shifted into the carry flag. Branches when the contents of the bit specified in the accumulator or memory is "0". Branches when the contents of the bit specified in the accumulator or memory is "1". Branches when the contents of carry flag is "0". Branches when the contents of carry flag is "1". Branches when the contents of zero flag is "1". 24 3 2 IMM # OP n 69 2 A # OP n 2 BIT, A # OP n ZP # OP n 65 3 BIT, ZP # OP n 2 #
ASL
C
7
0
0
BBC (Note 4) BBS (Note 4) BCC (Note 4) BCS (Note 4) BEQ (Note 4) BIT
Ab or Mb = 0?
Ab or Mb = 1?
C = 0?
C = 1?
Z = 1? V
A
M
BMI (Note 4) BNE (Note 4) BPL (Note 4) BRA
N = 1?
Z = 0?
N = 0? PC PC offset B1 M(S) PCH SS-1 M(S) PCL SS-1 M(S) PS SS-1 PCL ADL PCH ADH
BRK
3-60
V
When T = 1 M(X) M(X)
V
AND (Note 1)
When T = 0 AA M M
29 2
2
25 3
2
0A 2
1
06 5
2
13 + 20i
4
2
17 + 20i 07 + 20i
5
3
03 4 + 20i
2
5
3
"AND's" the contents of accumulator and memory. The results are not entered anywhere. Branches when the contents of negative flag is "1". Branches when the contents of zero flag is "0".
Branches when the contents of negative flag is "0". Jumps to address specified by adding offset to the program counter. Executes a software interrupt. 00 7 1
3807 GROUP USER'S MANUAL
APPENDIX
3.9 Machine instructions
Addressing mode ZP, X OP n 75 4 ZP, Y # OP n 2 ABS # OP n 6D 4 ABS, X # OP n 3 7D 5 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7
Processor status register 6 5 T * 4 B * 3 D * 2 I * 1 Z Z 0 C C
# OP n 3 79 5
# OP n 3
# OP n 61 6
# OP n 2 71 6
# OP n 2
NV NV
35 4
2
2D 4
3 3D 5
3 39 5
3
21 6
2 31 6
2
N
*
*
*
*
*
Z
*
16 6
2
0E 6
3 1E 7
3
N
*
*
*
*
*
Z
C
*
*
*
*
*
*
*
*
* 90 2
*
*
*
*
*
*
*
2
*
*
*
*
*
*
*
*
B0 2
2
*
*
*
*
*
*
*
*
F0 2 2C 4 3
2
*
*
*
*
*
*
*
*
M7 M6 *
*
*
*
Z
*
30 2
2
*
*
*
*
*
*
*
*
D0 2
2
*
*
*
*
*
*
*
*
10 2
2
*
*
*
*
*
*
*
*
80 4
2
*
*
*
*
*
*
*
*
*
*
*
1
*
1
*
*
3807 GROUP USER'S MANUAL
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APPENDIX
3.9 Machine instructions
Addressing mode Symbol Function Details IMP OP n BVC (Note 4) BVS (Note 4) CLB V = 0? Branches when the contents of overflow flag is "0". Branches when the contents of overflow flag is "1". Clears the contents of the bit specified in the accumulator or memory to "0". Clears the contents of the carry flag to "0". 18 2 1 1B 2 + 20i 1 1F 5 + 20i 2 IMM # OP n A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n #
V = 1? Ab or Mb 0 C0 D0 I0 T0 V0 When T = 0 A-M When T = 1 M(X) - M MM X-M
__
CLC
CLD
Clears the contents of decimal mode flag to "0". Clears the contents of interrupt disable flag to "0". Clears the contents of index X mode flag to "0". Clears the contents overflow flag to "0".
D8 2
1
CLI
58 2
1
CLT
12 2
1
CLV
B8 2
1
CMP (Note 3)
Compares the contents of accumulator and memory. Compares the contents of the memory specified by the addressing mode with the contents of the address indicated by index register X. Forms a one's complement of the contents of memory, and stores it into memory. Compares the contents of index register X and memory. Compares the contents of index register Y and memory. Decrements the contents of the accumulator or memory by 1. Decrements the contents of index register X CA 2 by 1. Decrements the contents of index register Y by 1. Divides the 16-bit data that is the contents of M (zz + x + 1) for high byte and the contents of M (zz + x) for low byte by the accumulator. Stores the quotient in the accumulator and the 1's complement of the remainder on the stack. "Exclusive-ORs" the contents of accumulator and memory. The results are stored in the accumulator. "Exclusive-ORs" the contents of the memory specified by the addressing mode and the contents of the memory at the address indicated by index register X. The results are stored into the memory at the address indicated by index register X. Increments the contents of accumulator or memory by 1. Increments the contents of index register X by 1. Increments the contents of index register Y by 1. E8 2 1 88 2 1
C9 2
2
C5 3
2
COM
44 5
2
CPX
E0 2
2
E4 3
2
CPY
Y-M A A - 1 or MM-1 XX-1 YY-1 A (M(zz + X + 1), M(zz + X)) / A M(S) 1's complememt of Remainder SS-1 When T = 0 - AAVM When T = 1 - M(X) M(X) V M
C0 2
2
C4 3
2
DEC
1A 2
1
C6 5
2
DEX
DEY
1
DIV
EOR (Note 1)
49 2
2
45 3
2
INC
A A + 1 or MM+1 XX+1 YY+1
3A 2
1
E6 5
2
INX
INY
C8 2
1
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3807 GROUP USER'S MANUAL
APPENDIX
3.9 Machine instructions
Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n 2 # 7
Processor status register 6 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C *
# OP n
# OP n
# OP n
# OP n
# OP n 50 2
NV * *
70 2
2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
*
*
*
*
0
*
*
*
*
*
*
*
*
0
*
*
*
*
0
*
*
*
*
*
* D5 4 CD 4
0
*
*
*
*
*
*
2
3 DD 5
3 D9 5
3
C1 6
2 D1 6
2
N
*
*
*
*
*
Z
C
N EC 4
*
*
*
*
*
Z
*
3
N
*
*
*
*
*
Z
C
CC 4
3
N
*
*
*
*
*
Z
C
D6 6
2
CE 6
3 DE 7
3
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
N E2 16 2
*
*
*
*
*
Z
*
*
*
*
*
*
*
*
*
55 4
2
4D 4
3 5D 5
3 59 5
3
41 6
2 51 6
2
N
*
*
*
*
*
Z
*
F6 6
2
EE 6
3 FE 7
3
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
3807 GROUP USER'S MANUAL
3-63
APPENDIX
3.9 Machine instructions
Addressing mode Symbol Function Details IMP OP n JMP If addressing mode is ABS PCL ADL PCH ADH If addressing mode is IND PCL M (ADH, ADL) PCH M (ADH, ADL + 1) If addressing mode is ZP, IND PCL M(00, ADL) PCH M(00, ADL + 1) M(S) PCH SS-1 M(S) PCL SS-1 After executing the above, if addressing mode is ABS, PCL ADL PCH ADH if addressing mode is SP, PCL ADL PCH FF If addressing mode is ZP, IND, PCL M(00, ADL) PCH M(00, ADL + 1) When T = 0 AM When T = 1 M(X) M M nn XM YM 7 0 0 C Jumps to the specified address. IMM # OP n A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n #
JSR
After storing contents of program counter in stack, and jumps to the specified address.
LDA (Note 2)
Load accumulator with contents of memory. Load memory indicated by index register X with contents of memory specified by the addressing mode. Load memory with immediate value.
A9 2
2
A5 3
2
LDM
3C 4
3
LDX
Load index register X with contents of memory. Load index register Y with contents of memory. Shift the contents of accumulator or memory to the right by one bit. The low order bit of accumulator or memory is stored in carry, 7th bit is cleared. Multiplies the accumulator with the contents of memory specified by the zero page X addressing mode and stores the high byte of the result on the stack and the low byte in the accumulator. No operation. EA 2 1
A2 2
2
A6 3
2
LDY
A0 2
2 4A 2 1
A4 3
2
LSR
46 5
2
MUL
M(S) * A A ! M(zz + X) SS-1
NOP
PC PC + 1 When T = 0 AAVM When T = 1 M(X) M(X) V M
ORA (Note 1)
"Logical OR's" the contents of memory and accumulator. The result is stored in the accumulator. "Logical OR's" the contents of memory indicated by index register X and contents of memory specified by the addressing mode. The result is stored in the memory specified by index register X.
09 2
2
05 3
2
3-64
3807 GROUP USER'S MANUAL
APPENDIX
3.9 Machine instructions
Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n 4C 3 ABS, X # OP n 3 ABS, Y IND ZP, IND # OP n 3 B2 4 IND, X IND, Y REL SP # OP n # 7
Processor status register 6 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C *
# OP n
# OP n 6C 5
# OP n 2
# OP n
# OP n
NV * *
20 6
3
02 7
2
22 5
2
*
*
*
*
*
*
*
*
B5 4
2
AD 4
3 BD 5
3 B9 5
3
A1 6
2 B1 6
2
N
*
*
*
*
*
Z
*
*
*
*
*
*
*
*
*
B6 4 B4 4 56 6
2 AE 4 AC 4 4E 6
3
BE 5
3
N
*
*
*
*
*
Z
*
2
3 BC 5
3
N
*
*
*
*
*
Z
*
2
3 5E 7
3
0
*
*
*
*
*
Z
C
62 15 2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
15 4
2
0D 4
3 1D 5
3 19 5
3
01 6
2 11 6
2
N
*
*
*
*
*
Z
*
3807 GROUP USER'S MANUAL
3-65
APPENDIX
3.9 Machine instructions
Addressing mode Symbol Function Details IMP OP n PHA M(S) A SS-1 Saves the contents of the accumulator in memory at the address indicated by the stack pointer and decrements the contents of stack pointer by 1. Saves the contents of the processor status register in memory at the address indicated by the stack pointer and decrements the contents of the stack pointer by 1. Increments the contents of the stack pointer by 1 and restores the accumulator from the memory at the address indicated by the stack pointer. Increments the contents of stack pointer by 1 and restores the processor status register from the memory at the address indicated by the stack pointer. Shifts the contents of the memory or accumulator to the left by one bit. The high order bit is shifted into the carry flag and the carry flag is shifted into the low order bit. Shifts the contents of the memory or accumulator to the right by one bit. The low order bit is shifted into the carry flag and the carry flag is shifted into the high order bit. Rotates the contents of memory to the right by 4 bits. 40 6 1 48 3 IMM # OP n 1 A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n #
PHP
M(S) PS SS-1
08 3
1
PLA
SS+1 A M(S)
68 4
1
PLP
SS+1 PS M(S)
28 4
1
ROL
7
0 C
2A 2
1
26 5
2
ROR
7 C
0
6A 2
1
66 5
2
RRF
7 SS+1 PS M(S) SS+1 PCL M(S) SS+1 PCH M(S) SS+1 PCL M(S) SS+1 PCH M(S)
0
82 8
2
RTI
Returns from an interrupt routine to the main routine.
RTS
Returns from a subroutine to the main routine.
60 6
1
SBC (Note 1) (Note 5)
When T = 0 _ AA-M-C When T = 1 _ M(X) M(X) - M - C
Subtracts the contents of memory and complement of carry flag from the contents of accumulator. The results are stored into the accumulator. Subtracts contents of complement of carry flag and contents of the memory indicated by the addressing mode from the memory at the address indicated by index register X. The results are stored into the memory of the address indicated by index register X. Sets the specified bit in the accumulator or memory to "1". Sets the contents of the carry flag to "1". 38 2 1
E9 2
2
E5 3
2
SEB
Ab or Mb 1 C1 D1 I1 T1
0B 2 + 20i
1
0F 5 + 20i
2
SEC
SED
Sets the contents of the decimal mode flag to "1". Sets the contents of the interrupt disable flag to "1". Sets the contents of the index X mode flag to "1".
F8 2
1
SEI
78 2
1
SET
32 2
1
3-66
3807 GROUP USER'S MANUAL
APPENDIX
3.9 Machine instructions
Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7
Processor status register 6 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C *
# OP n
# OP n
# OP n
# OP n
# OP n
NV * *
*
*
*
*
*
*
*
*
N
*
*
*
*
*
Z
*
(Value saved in stack)
36 6
2
2E 6
3 3E 7
3
N
*
*
*
*
*
Z
C
76 6
2
6E 6
3 7E 7
3
N
*
*
*
*
*
Z
C
*
*
*
*
*
*
*
*
(Value saved in stack)
*
*
*
*
*
*
*
*
F5 4
2
ED 4
3 FD 5
3 F9 5
3
E1 6
2 F1 6
2
NV
*
*
*
*
Z
C
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
*
*
*
*
1
*
*
*
*
*
*
*
*
1
*
*
*
*
1
*
*
*
*
*
3807 GROUP USER'S MANUAL
3-67
APPENDIX
3.9 Machine instructions
Addressing mode Symbol Function Details IMP OP n STA MA Stores the contents of accumulator in memory. IMM # OP n A # OP n BIT, A # OP n ZP # OP n 85 4 42 2 BIT, ZP # OP n 2 #
STP MX MY XA YA M = 0? XS AX SX AY
Stops the oscillator.
1
STX
Stores the contents of index register X in memory. Stores the contents of index register Y in memory. Transfers the contents of the accumulator to AA 2 index register X. Transfers the contents of the accumulator to A8 2 index register Y. Tests whether the contents of memory are "0" or not. Transfers the contents of the stack pointer to BA 2 index register X. Transfers the contents of index register X to 8A 2 the accumulator. Transfers the contents of index register X to 9A 2 the stack pointer. Transfers the contents of index register Y to the accumulator. Stops the internal clock. 98 2 1 1
86 4 84 4
2
STY
2
TAX
TAY
1
TST
64 3
2
TSX
TXA
1
TXS
1
TYA
1
WIT Notes 1 2 3 4 5
C2 2
1
: The number of cycles "n" is increased by 3 when T is 1. : The number of cycles "n" is increased by 2 when T is 1. : The number of cycles "n" is increased by 1 when T is 1. : The number of cycles "n" is increased by 2 when branching has occurred. : N, V, and Z flags are invalid in decimal operation mode.
3-68
3807 GROUP USER'S MANUAL
APPENDIX
3.9 Machine instructions
Addressing mode ZP, X OP n 95 5 ZP, Y # OP n 2 ABS # OP n 8D 5 ABS, X # OP n 3 9D 6 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7
Processor status register 6 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C *
# OP n 3 99 6
# OP n 3
# OP n 81 7
# OP n 2 91 7
# OP n 2
NV * *
*
*
*
*
*
*
*
*
96 5
2 8E 5
3
*
*
*
*
*
*
*
*
94 5
2
8C 5
3
*
*
*
*
*
*
*
*
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
*
*
*
*
*
*
*
*
N
*
*
*
*
*
Z
*
*
*
*
*
*
*
*
*
Symbol IMP IMM A BIT, A ZP BIT, ZP ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP C Z I D B T V N
Contents Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit relative addressing mode Zero page addressing mode Zero page bit relative addressing mode Zero page X addressing mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode Special page addressing mode Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag X-modified arithmetic mode flag Overflow flag Negative flag + - V - V - X Y S PC PS PCH PCL ADH ADL FF nn M V
Symbol
Contents Addition Subtraction Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high-order bits of program counter 8 low-order bits of program counter 8 high-order bits of address 8 low-order bits of address FF in Hexadecimal notation Immediate value Memory specified by address designation of any addressing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by ADH and ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits. Contents of address indicated by zero page ADL 1 bit of accumulator 1 bit of memory Opcode Number of cycles Number of bytes
M(X) M(S) M(ADH, ADL)
M(00, ADL) Ab Mb OP n #
3807 GROUP USER'S MANUAL
3-69
APPENDIX
3.10 List of instruction codes
3.10 List of instruction codes
D3 - D0 Hexadecimal notation 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
D7 - D4
0
1
2
3 BBS 0, A BBC 0, A BBS 1, A BBC 1, A BBS 2, A BBC 2, A BBS 3, A BBC 3, A BBS 4, A BBC 4, A BBS 5, A BBC 5, A BBS 6, A BBC 6, A BBS 7, A BBC 7, A
4
5 ORA ZP ORA ZP, X AND ZP AND ZP, X EOR ZP EOR ZP, X ADC ZP ADC ZP, X STA ZP STA ZP, X LDA ZP LDA ZP, X CMP ZP CMP ZP, X SBC ZP SBC ZP, X
6 ASL ZP ASL ZP, X ROL ZP ROL ZP, X LSR ZP LSR ZP, X ROR ZP ROR ZP, X STX ZP STX ZP, Y LDX ZP LDX ZP, Y DEC ZP DEC ZP, X INC ZP INC ZP, X
7 BBS 0, ZP BBC 0, ZP BBS 1, ZP BBC 1, ZP BBS 2, ZP BBC 2, ZP BBS 3, ZP BBC 3, ZP BBS 4, ZP BBC 4, ZP BBS 5, ZP BBC 5, ZP BBS 6, ZP BBC 6, ZP BBS 7, ZP BBC 7, ZP
8
9 ORA IMM ORA ABS, Y AND IMM AND ABS, Y EOR IMM EOR ABS, Y ADC IMM ADC ABS, Y -- STA ABS, Y LDA IMM LDA ABS, Y CMP IMM CMP ABS, Y SBC IMM SBC ABS, Y
A ASL A DEC A ROL A INC A LSR A -- ROR A --
B SEB 0, A CLB 0, A SEB 1, A CLB 1, A SEB 2, A CLB 2, A SEB 3, A CLB 3, A SEB 4, A CLB 4, A SEB 5, A CLB 5, A SEB 6, A CLB 6, A SEB 7, A CLB 7, A
C
D ORA ABS
E ASL ABS
F SEB 0, ZP
0000
BRK
JSR ORA IND, X ZP, IND ORA IND, Y AND IND, X AND IND, Y EOR IND, X EOR IND, Y CLT JSR SP SET
--
PHP
--
0001
1
BPL JSR ABS BMI
-- BIT ZP -- COM ZP -- TST ZP -- STY ZP STY ZP, X LDY ZP LDY ZP, X CPY ZP -- CPX ZP --
CLC
-- BIT ABS LDM ZP JMP ABS -- JMP IND -- STY ABS -- LDY ABS
CLB ASL ORA ABS, X ABS, X 0, ZP AND ABS ROL ABS SEB 1, ZP
0010
2
PLP
0011
3
SEC
CLB ROL AND ABS, X ABS, X 1, ZP EOR ABS LSR ABS SEB 2, ZP
0100
4
RTI
STP
PHA
0101
5
BVC
--
CLI
CLB LSR EOR ABS, X ABS, X 2, ZP ADC ABS ROR ABS SEB 3, ZP
0110
6
RTS
ADC MUL IND, X ZP, X ADC IND, Y STA IND, X STA IND, Y LDA IND, X -- RRF ZP -- LDX IMM
PLA
0111
7
BVS
SEI
CLB ROR ADC ABS, X ABS, X 3, ZP STA ABS STA ABS, X LDA ABS STX ABS -- LDX ABS SEB 4, ZP CLB 4, ZP SEB 5, ZP
1000
8
BRA
DEY
TXA
1001
9
BCC LDY IMM BCS CPY IMM BNE CPX IMM BEQ
TYA
TXS
1010
A
TAY
TAX
1011
B
LDA JMP IND, Y ZP, IND CMP IND, X CMP IND, Y WIT
CLV
TSX
CLB LDX LDA LDY ABS, X ABS, X ABS, Y 5, ZP CPY ABS -- CPX ABS -- CMP ABS DEC ABS SEB 6, ZP
1100
C
INY
DEX
1101
D
--
CLD
--
CLB DEC CMP ABS, X ABS, X 6, ZP SBC ABS INC ABS SEB 7, ZP
1110
E
SBC DIV IND, X ZP, X SBC IND, Y --
INX
NOP
1111
F
SED
--
CLB INC SBC ABS, X ABS, X 7, ZP
3-byte instruction 2-byte instruction 1-byte instruction
3-70
3807 GROUP USER'S MANUAL
APPENDIX
3.11 SFR memory map
3.11 SFR memory map
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D)
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316
Timer X (low-order) (TXL) Timer X (high-order) (TXH) Timer Y (low-order) (TYL) Timer Y (high-order) (TYH) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer X mode register (TXM) Timer Y mode register (TYM) Timer 123 mode register (T123M) Real time port register (RTP) Real time port control register 0 (RTPCON0) Real time port control register 1 (RTPCON1) Real time port control register 2 (RTPCON2) Real time port control register 3 (RTPCON3) Timer A (low-order) (TAL) Timer A (high-order) (TAH) Timer B (low-order) (TBL) Timer B (high-order) (TBH) D-A control register (DACON) A-D control register (ADCON) A-D conversion register (AD) D-A1 conversion register (DA1) D-A2 conversion register (DA2) D-A3 conversion register (DA3) D-A4 conversion register (DA4)
Interrupt edge selection register (INTEDGE)
Timer XY control register (TXYCON) Port P2P3 control register (P2P3C) Pull-up control register (PULL) Watchdog timer control register (WDTCON) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register 1 (SIO2CON1) Serial I/O2 control register 2 (SIO2CON2) Serial I/O2 register (SIO2)
003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Interrupt control register 2(ICON2)
3807 GROUP USER'S MANUAL
3-71
3-72
P87/RTP5 P86/RTP4 P85/RTP3 P84/RTP2 P83/RTP1 P82/RTP0 P81/DA4/AN12 P80/DA3/AN11 VCC ADVREF AVSS P65/DAVREF/AN10 P64/CMPREF /AN9 P63/CMPIN /AN8 CMPOUT CMPVCC
79 80
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
APPENDIX
3.12 Pin configuration
3.12 Pin configuration
78
77
76
75
74
73
72
71
70
69
68
67
66
65
M38073M4-XXXFP
3807 GROUP USER'S MANUAL
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P62/AN7 P61/AN6 P60/AN5 P77/AN4 P76/AN3 P75/AN2 P74/AN1 P73/SRDY2/ADT/AN0 P72/SCLK2 P71/SOUT2 P70/SIN2 P57/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/INT4 P52/INT3 P51/SCMP2/INT2 P50/TOUT P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT1
P30/RTP6 P31/RTP7 P32/ONW P33/RESETOUT P34/CKOUT/ P35/SYNC P36/WR P37/RD P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13 P16/AD14 P17/AD15
P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 VSS XOUT XIN P40/XCOUT P41/XCIN RESET CNVSS P42/INT0
MITSUBISHI SEMICONDUCTORS USER'S MANUAL 3807 Group
Nov. First Edition 1996 Editioned by Committee of editing of Mitsubishi Semiconductor USER'S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.
(c)1996 MITSUBISHI ELECTRIC CORPORATION
User's Manual 3807 Group
H-EF458-A KI-9611 Printed in Japan (ROD) (c) 1996 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective Nov. 1996. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.0 First Edition Revision Description
3807 Group User's Manual
Rev. date 971101
(1/1)

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